71_alarm_counter.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--                             _ _
--                              L   
---------------------------OO-------OO---------------------------------
--                                                                   --
-- DESCRIPTION : training files                                      --
-- Author      : Chen DongYing & Zhang DongXiao                      --
-- AFFILIATION : ASIC Research Center of B.I.T.                      --
-- DATE        : 1999.06 14-20                                       --
-- COPYRIGHT   : (c) 1999-2001, Mentor China                         --
--                              ASIC Research Center of B.I.T.       --
--                                                                   --
-- This source file may be used and distributed without restriction  --
-- provided that this copyright statement is not removed  from  the  --
-- file and that any derivative work contains this copyright notice. --
--                                                                   --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

-----------------------
entity alarm_counter is
-----------------------
   port(new_current_time:in  t_clock_time;
        load_new_c      :in  std_logic;
        clk             :in  std_logic;
        reset           :in  std_logic;
        current_time    :out t_clock_time
		);
end alarm_counter;

architecture rtl of alarm_counter is
   signal i_current_time : t_clock_time;
begin
   process(clk,reset,load_new_c)
      variable c_t:t_clock_time;
   begin
      if reset = '1' then
         i_current_time <= (0,0,0,0);
      elsif load_new_c = '1' then
            i_current_time <= new_current_time;
      elsif rising_edge(clk) then
            c_t := i_current_time;
            if c_t(0) < 9 then             
               c_t(0) := c_t(0) + 1;
            else        
               c_t(0) := 0;
               if c_t(1) < 5 then
                  c_t(1) := c_t(1) + 1;
               else
                  c_t(1) := 0;
                  if c_t(3) < 2 then
                     if c_t(2) < 9 then
                        c_t(2) := c_t(2) + 1;
                     else
                        c_t(2) := 0;
                        c_t(3) := c_t(3) + 1;
                     end if;
                  else
                     if c_t(2) < 3 then
                        c_t(2) := c_t(2) + 1;
                     else
                        c_t(2) := 0;
                        c_t(3) := 0;
                     end if;
                  end if;
               end if;
            end if;
            i_current_time <= c_t;
         end if;

   end process;

   current_time <= i_current_time;
end rtl;