51_test_113.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--Page          :291,292

--Objective     :Transport driver preemption 

--Filename      :test_113.vhd

--Author        :Joseph Pick

entity Test_113 is
end Test_113;

architecture Behave_1 of Test_113 is
  signal A : BIT := '1';
  signal B : BIT := '1';
  signal C : BIT := '1';

  function Delay(Value : BIT ;Ph1 :TIME;P1h :TIME )
				  return TIME is
  begin
	  if Value = '1' then 
		return P1h;
      else 
		return Ph1;
   	  end if;
  end Delay;
begin 

  Schedule_A:
  process
  begin
	wait on B,C;
	A <= transport B and C after Delay(B and C ,16 ns , 10 ns);
  end process Schedule_A;

  Analysis_A:
  process 
	variable Var_A : BIT := '0';
  begin 
	wait on A'TRANSACTION;
	Var_A := A;
  end process Analysis_A;
   
  B <= '0' after 10 ns ,'1'after 12 ns;
end Behave_1;