90_wss_subtype.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--这是子类型和部件声明的包
--用于区分向量类型的不同宽度
LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.std_logic_arith.ALL;

  PACKAGE pkg_types IS

		  SUBTYPE bit1    IS std_ulogic;

          SUBTYPE bit2    IS std_ulogic_vector( 1 DOWNTO 0);
          SUBTYPE bit3    IS std_ulogic_vector( 2 DOWNTO 0);
		  SUBTYPE bit4    IS std_ulogic_vector( 3 DOWNTO 0);
		  SUBTYPE bit5    IS std_ulogic_vector( 4 DOWNTO 0);
		  SUBTYPE bit8    IS std_ulogic_vector( 7 DOWNTO 0);
		  SUBTYPE bit11   IS std_ulogic_vector(10 DOWNTO 0);

		  SUBTYPE bit2_r  IS std_logic_vector ( 1 DOWNTO 0);
		  SUBTYPE bit3_r  IS std_logic_vector ( 2 DOWNTO 0);
		  SUBTYPE bit4_r  IS std_logic_vector ( 3 DOWNTO 0);
		  SUBTYPE bit5_r  IS std_logic_vector ( 4 DOWNTO 0);
		  SUBTYPE bit8_r  IS std_logic_vector ( 7 DOWNTO 0);
		  SUBTYPE bit11_r IS std_logic_vector (10 DOWNTO 0);

END pkg_types;