42_mix.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library IEEE;
use IEEE.std_logic_1164.all;
library dsp_lib;
use dsp_lib.delay_macro.all;
use dsp_lib.logic_pack.all;
use dsp_lib.const_pack.all;

---------------------------------------------------
entity wst0intm is
--------------------------------------------------
	port(
			i13  :  in std_logic;

			i19  :  in std_logic;
			i30  :  in std_logic;
			b53  :  in std_logic;
			i18  :  in std_logic;

			b72  :  in std_logic;
   			i5   :  in std_logic;
			-----------------------
			k38  :  out std_logic;
			st0intm  :  out std_logic
		);
end wst0intm;

architecture struc of wst0intm is

	-----------------------
	component wa
	-----------------------
		port(
				inn  :  in std_logic;
				b53  :  in std_logic;
				-----------------------
				outt :  out std_logic
			);
	end component;

signal out1  :  std_logic;

begin

	U1 : wa
		port map(i18,b53,out1);
	
	process
		variable ic : std_logic;
		variable id : std_logic;
		begin 
			id := i19 & i30 & out1
			case id is
				when "100" =>
					ic := '1';
				when "010" =>
					ic := '0';
				when "001" =>
					ic := i13;
				when others => NULL;
			end case;
			if b72 = '1' then
				st0intm <= ic after CMOS_DELAY;
			end if;
			if i5 = '1' then
				if ic = '0' then
					k38 <= '0';
				else k38 <= k38;
				end if;
			end if;
    end process;

end struc;