69_decoder.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--                             _ _
--                              L   
---------------------------OO-------OO---------------------------------
--                                                                   --
-- DESCRIPTION : training files                                      --
-- Author      : Chen DongYing & Zhang DongXiao                      --
-- AFFILIATION : ASIC Research Center of B.I.T.                      --
-- DATE        : 1999.06 14-20                                       --
-- COPYRIGHT   : (c) 1999-2001, Mentor China                         --
--                              ASIC Research Center of B.I.T.       --
--                                                                   --
-- This source file may be used and distributed without restriction  --
-- provided that this copyright statement is not removed  from  the  --
-- file and that any derivative work contains this copyright notice. --
--                                                                   --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;

-----------------
entity decoder is 
-----------------
port(
	keypad :in  std_logic_vector(9 downto 0);
    value  :out t_digital
	);
end decoder;

architecture rtl of decoder is
begin
   with keypad select
   value <= 0  when "0000000001",
            1  when "0000000010", 
            2  when "0000000100", 
            3  when "0000001000", 
            4  when "0000010000", 
            5  when "0000100000", 
            6  when "0001000000", 
            7  when "0010000000", 
            8  when "0100000000", 
            9  when "1000000000", 
			0  when others;
 end rtl;