41_generic_testbench.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library IEEE;
use IEEE.std_logic_1164.all;

entity test_decoder3 is
end test_decoder3;

architecture BENCH of test_decoder3 is
component decoder3
	port(
		 Sel : Bit_vector ( 1 to 3 );
		 Dout : out Bit_vector ( 1 to 8 ));
end component;

for all : decoder3 use entity work.decoder(Generic_structure)
                                    generic map (3)
			       port map ( Sel, Dout);

  signal t_S : Bit_vector( 1 to 3 );
  signal t_O : Bit_vector( 1 to 8 );

  begin
     I1 : decoder3
          port map (
                     Sel=>t_S ,
                      Dout=>t_O );

     driver: process
     begin
         t_S <= "000",
                "001" after 100 ns,     
                "010" after 200 ns,     
                "011" after 300 ns,     
                "100" after 400 ns,     
                "101" after 500 ns,     
                "110" after 600 ns,     
                "111" after 700 ns;
          wait for 2 us;
          assert false
           report "-----End of Simulation------" 
           severity error;
      end process;
 
  end BENCH;