57_instruction_dec.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--Page          :303 304

--Objective     :Efficient command decoding

--Filename      :test_67b.vhd

--Author        :Joseph Pick

entity Test_67b is
end Test_67b;

architecture Behave_1 of Test_67b is

  type Instruction_Enum is (ADD,SUBTRACT,MULTIPLY);
  signal Command_Nat :NATURAL := 0 ;

begin 
 
  Proc_Execute:
  process
	variable Count_A : Natural := 5;
	variable Count_B : Natural := 2;
	variable Result  : Natural := 0;
	variable Command_Enum : Instruction_Enum;

  begin 
	-- In practise the command will be a bit string that must 
	-- be converted into a NATURAL number.
	wait on Command_Nat;

	--Confirm that the converted NATURAL number will correctly,
	--map onto an enumberation literal.
	if (Command_Nat >= 0) and (Command_Nat <= 2) then 
	  --Convert this NATURAL number into the 
	  --corresponding enumberation literal.
	  Command_Enum := Instruction_Enum'VAL(Command_Nat);
 	else 

	  assert FALSE
		report "Invalid command code sequence"
		severity ERROR;
    end if;

	case Command_Enum is 
	   when ADD => Result :=Count_A + Count_B ;
	   when SUBTRACT => Result := Count_A - Count_B ;
	   when MULTIPLY => Result := Count_A * Count_B ;
	end case;
  end process Proc_Execute;

  Gen_Command:
  Command_Nat <= 1 after 10 ns,0 after 20 ns ,2 after 30 ns,
				 0 after 40 ns,1 after 50 ns ;
end Behave_1;