93_wss.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--wss为一个组装程序，把mem_string,mem_sequence,co_processor
--和top controller组装为一个系统
LIBRARY ieee;
   USE ieee.std_logic_1164.ALL;
   USE ieee.std_logic_arith.ALL;
   --USE ieee.std_logic_unsigned.ALL;
   USE work.PKG_types.ALL;
   USE work.pkg_components.ALL;
  
ENTITY wss IS 
PORT ( 
       reset       : IN   bit1;
       clk         : IN   bit1;
       command     : IN   bit1;
       c_req       : OUT  bit1;
       c_ack       : IN   bit1;
       c_vaild     : IN   bit1;
       s_req       : out  bit1;
       s_ack       :in    bit1;
       s_valid     : in   bit1;
       data_in     : IN   bit8;
       dmin        : OUT  bit11;
       vector      : OUT  bit4; 
       status      : OUT  bit1);
END wss;

ARCHITECTURE rt1 OF wss IS
CONSTANT n                  : integer:=2;
SIGNAL  c_sel,c_done        : bit1;
SIGNAL  s_sel,s_done        : bit1;
SIGNAL  p_sel,done0,done1   : bit1;
SIGNAL  mode,sel_read       : bit1;
SIGNAL  burst               : bit2_r;
SIGNAL  s_ad                : bit5;
SIGNAL  c_ad                : bit3;
SIGNAL  s,c                 : bit8;

BEGIN
 tp : top
 PORT MAP (clk,reset,command,c_sel,s_sel,burst,p_sel,mode,c_done,s_done,done0,done1,status);
 mq : mem_sequence
 PORT MAP (clk,reset,sel_read, c_sel,c_req,c_ack,c_vaild,data_in,c_ad,c,c_done);

 mt : mem_string
 PORT MAP (clk,reset,sel_read,s_sel,burst,s_req,s_ack,s_valid,data_in,s_ad,s,s_done);

 pr :co_processor
 PORT MAP (clk,reset,c,s,p_sel,mode,sel_read,c_ad,s_ad,dmin,vector,done0,done1);
END rt1;