30_test_3.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Page		 	: 278 - 278
--
-- Objective 	: wait until...
--
-- File Name 	: test_3.vhd
--
-- Author    	: Joseph Pick
--

entity Test_3 is
end Test_3;

architecture Behave_1 of Test_3 is
	signal Sample : BIT;
begin

	Sender:
	process
	begin
		Sample <= '1';
		wait for 20 ns;
		assert FALSE
			report "Terminated in Sender"
			severity NOTE;
		wait;
	end process;

	Recevier:
	process
	begin 
		wait for 10 ns;
		wait until Sample = '1';
		assert FALSE
			report "Terminated in Receiver"
			severity NOTE;
		wait;
	end process;

end Behave_1;