36_test.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library ieee;
use ieee.std_logic_1164.all;

entity gcd_tester is
end gcd_tester;

architecture test of gcd_tester is
signal start:bit :='0';
signal clk:bit :='0';
signal din:bit :='0';
signal xi:integer :=4;
signal yi:integer :=8;
signal dout:bit :='0';
signal output:integer :=0;

component gcd 
 port (start:in bit;
	   clk:in bit;
	   din:in bit;
	   xi,yi:in integer;
	   dout:out bit;
	   output:out integer
      );  
end component;

begin
 gcd1:gcd port map (start,clk,din,xi,yi,dout,output);
 process 
 begin
	 clk <= not clk; --after half period;
 wait for 10ns; 
 end process;
 process
 begin
 wait for 50ns;
	 start <='1';
	 din <='1' ;

	 wait for 100 ns;
	 start <='0';
	 din <='0';
	 wait for 100 ns;
 xi <=9;
 yi <=3;
 start <='1';
 din <='1';
 wait for 100ns;
 start <='0';
 din <='0';
 wait for 100ns;
end process;
end test;