68_alarm_controller.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--                             _ _
--                              L   
---------------------------OO-------OO---------------------------------
--                                                                   --
-- DESCRIPTION : training files                                      --
-- Author      : Chen DongYing & Zhang DongXiao                      --
-- AFFILIATION : ASIC Research Center of B.I.T.                      --
-- DATE        : 1999.06 14-20                                       --
-- COPYRIGHT   : (c) 1999-2001, Mentor China                         --
--                              ASIC Research Center of B.I.T.       --
--                                                                   --
-- This source file may be used and distributed without restriction  --
-- provided that this copyright statement is not removed  from  the  --
-- file and that any derivative work contains this copyright notice. --
--                                                                   --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

entity alarm_controller is
port(key           :in std_logic;
     alarm_button  :in std_logic;
     time_button   :in std_logic;
     clk           :in std_logic;
     reset         :in std_logic;
     load_new_a    :out std_logic;
     load_new_c    :out std_logic;
     show_new_time :out std_logic;
     show_a        :out std_logic
     );
end alarm_controller;

architecture rtl of alarm_controller is
   --
   -- type
   --
   type     t_state is (s0, s1, s2, s3,s4);
   --
   -- constant
   -- time out : if clock period is 10 ms , the
   -- following timeout will be 5 s
   --
   constant key_timeout        : t_short := 500;
   constant show_alarm_timeout : t_short := 500;
   --
   -- inner sigals
   --
   signal curr_state     : t_state;
   signal next_state     : t_state;
   --
   signal counter_k      : t_short;
   signal enable_count_k : std_logic;
   signal count_k_end    : std_logic;
   --
   signal counter_a      : t_short;
   signal enable_count_a : std_logic;
   signal count_a_end    : std_logic;
begin
process(clk,reset)
begin
   if reset = '1' then
      curr_state <= s0;
   elsif rising_edge(clk) then
      curr_state <= next_state;
   end if;    
end process;

process(key, alarm_button, time_button, curr_state, 
		count_a_end,count_k_end)
begin
   -- initializtion
   next_state     <= curr_state;
   load_new_a     <= '0';
   load_new_c     <= '0';
   show_a         <= '0';
   show_new_time  <= '0';
   enable_count_k <= '0';
   enable_count_a <= '0';
   --
   case curr_state is
   when s0 =>                 -- initial state
       -- next state ?
       if (key = '1') then
          next_state <= s1;
          show_new_time <= '1';
       elsif (alarm_button = '1') then
          next_state <= s4;
          show_a <= '1';
       else 
          next_state <= s0;
       end if;
   when s1 =>                 -- key has been pressed
       -- next state ?
       if (key = '1') then
          next_state <= s1;
       elsif (alarm_button = '1') then
          next_state <= s2;
          load_new_a <= '1';
       elsif (time_button = '1') then
          next_state <= s3;
          load_new_c <= '1';
       else
          if (count_k_end = '1') then  -- time out ?
              next_state <= s0;
          else
              next_state <= s1;
          end if;
              enable_count_k <= '1';
       end if;
       --
       show_new_time  <= '1';
   when s2 =>                -- load new alarm
       -- next state?
       if (alarm_button = '1') then
          next_state <= s2;
          load_new_a <= '1';
       else
          next_state <= s0; -- return
       end if;
       -- signals
   when s3 =>                -- load new time 
       -- next state?
       if (time_button = '1') then
          next_state <= s3;
          load_new_c  <= '1';
       else
          next_state <= s0; -- return
       end if;
       -- signals
   when s4 =>                -- show alarm
       -- next state?
       if (key = '1') then
          next_state <= s1;
       else
          next_state     <= s4;
          if (count_a_end = '1') then
             next_state <= s0;
          else 
             next_state <= s4;
       	     show_a <= '1';
	  end if;
	  enable_count_a <= '1';
       end if;
       -- signals
   when others =>
       null;
   end case;
end process;
    
--
-- 	counter for incrementing key 
--
count_key : process(enable_count_k, clk)
begin
   if (enable_count_k = '0') then
      counter_k   <= 0;
      count_k_end <= '0';
   elsif (rising_edge(clk)) then
      if (counter_k >= key_timeout) then -- time out ?
         count_k_end <= '1';
      else
         counter_k <= counter_k + 1;
      end if;
   end if;
end process;

--
-- 	counter for incrementing show alarm time
--
count_alarm : process(enable_count_a, clk)
begin
   if (enable_count_a = '0') then
      counter_a   <= 0;
      count_a_end <= '0';
   elsif rising_edge(clk) then
      if (counter_a >= show_alarm_timeout) then -- time out ?
         count_a_end <= '1';
      else
         counter_a <= counter_a + 1;
      end if;
   end if;
end process;

end rtl;