68_tb_alarm_controller.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library ieee;
use ieee.std_logic_1164.all;

entity tb_alarm_controller is
end tb_alarm_controller;

use work.p_alarm.all;

architecture test of tb_alarm_controller is
component alarm_controller_bench
port(
     key           :in  std_logic;
     alarm_button  :in  std_logic;
     time_button   :in  std_logic;
     clk           :in  std_logic;
     reset         :in  std_logic;
     load_new_a    :out std_logic;
     load_new_c    :out std_logic;
     show_new_time :out std_logic;
     show_a        :out std_logic);
end component;

signal key           : std_logic:='0';
signal alarm_button  : std_logic:='0';
signal time_button   : std_logic:='0';
signal clk           : std_logic:='0';
signal reset         : std_logic:='0';
signal load_new_a    : std_logic:='0';
signal load_new_c    : std_logic:='0';
signal show_new_time : std_logic:='0';
signal show_a        : std_logic:='0';

for all: alarm_controller_bench use entity work.alarm_controller(rtl);

begin
u1: alarm_controller_bench 
    port map(key,
             alarm_button,
             time_button,
             clk,
             reset,
             load_new_a,
             load_new_c,
			 show_new_time,
             show_a
             );

process
begin
   wait until clk = '1';
   wait until clk = '1';
   --------------------------------------
   -- check load new alarm
   --------------------------------------
   --       key stroke 1   -- eg input 1
   key <= '1';
   wait until clk = '1';
   wait until clk = '1';
   key <= '0';
   --       key stroke 2   -- eg input 2
   key <= '1';
   wait until clk = '1';
   wait until clk = '1';
   key <= '0';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
   alarm_button <= '1';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
   alarm_button <= '0';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
  
   --------------------------------------
   -- check load new time
   --------------------------------------
   --       key stroke 1   -- eg input 1
   key <= '1';
   wait until clk = '1';
   wait until clk = '1';
   key <= '0';
   --       key stroke 2   -- eg input 2
   wait until clk = '1';
   wait until clk = '1';
   key <= '1';
   wait until clk = '1';
   wait until clk = '1';
   key <= '0';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
   time_button <= '1';
   wait until clk = '1';
   wait until clk = '1';
   wait until clk = '1';
   time_button <= '0';
   wait until clk = '1';
   wait until clk = '1';
   

   --------------------------------------
   -- check time delay out
   --------------------------------------
   key <= '1';
   wait until clk = '1';
   wait until clk = '1';
   key <= '0';
   wait for 10 sec;

   
   --------------------------------------
   -- check show alarm (out)
   --------------------------------------
   wait until clk = '1';
   alarm_button <= '1';
   wait until clk = '1';
   wait until clk = '1';
   alarm_button <= '0';
   wait for 8 sec;
   --------------------------------------
   -- the following is just to stop 
   --------------------------------------
   assert false report "End of simulation!"
   severity error;
end process;
     
clk <= not clk after 5 ms;
end test;