43_test_register.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--******************************************
--  Test Bench
--  Name    : 	test_register.vhd
--  Purpose : 	test 4-bit register  
--  Author :	Liu Qinnan
--  Time	:	1998,9,29
--******************************************


library work;
use work.shift_types.all;

library ieee;
use ieee.std_logic_1164.all;

entity test_shifter is
end test_shifter;

architecture BENCH of test_shifter is
	component shifter
		port(
		din: in bit4;
		clk,load,left_right: in std_logic;
		dout: inout bit4);
	end component;
	
	signal din: bit4;
	signal clk: std_logic;
	signal load: std_logic;
	signal left_right: std_logic;
	signal dout: bit4;

	for all: shifter use entity work.shifter(synth);
	begin
	shifter1:shifter
		port map(
		din,
		clk,
		load,
		left_right,
		dout);

shift_driver:process
begin 

-----------------------------
--#####     pattern 1     #####
----------------------------
--set load ='1' , input din to shift_val
clk <= '0';
load <= '1';
din <= "0001";
wait for 5 ns;

--put shift_val to dout 
clk <= '1';
wait for 5 ns;

--shift_to _right 
clk <= '0';
load <='0';
left_right <= '0';
wait for 5 ns;

--put result to dout
clk <= '1';
wait for 5 ns;


assert (din/= "0000")
report("assert1 din/= 0000")
severity warning;


-----------------------------
--#####     pattern 2     #####
----------------------------
--set load ='1' , input din to shift_val
clk <= '0';
load <= '1';
din <= "0010";
wait for 5 ns;

--put shift_val to dout 
clk <= '1';
wait for 5 ns;

--shift_to _right 
clk <= '0';
load <='0';
left_right <= '0';
wait for 5 ns;

--put result to dout
clk <= '1';
wait for 5 ns;


assert (din/= "0001")
report("assert2 din/= 0001")
severity warning;



-----------------------------
--#####     pattern 1     #####
----------------------------
--set load ='1' , input din to shift_val
clk <= '0';
load <= '1';
din <= "0100";
wait for 5 ns;

--put shift_val to dout 
clk <= '1';
wait for 5 ns;

--shift_to _right 
clk <= '0';
load <='0';
left_right <= '0';
wait for 5 ns;

--put result to dout
clk <= '1';
wait for 5 ns;


assert (din/= "0010")
report("assert1 din/= 0010")
severity warning;

-----------------------------
--#####     pattern 4     #####
----------------------------
--set load ='1' , input din to shift_val
clk <= '0';
load <= '1';
din <= "1000";
wait for 5 ns;

--put shift_val to dout 
clk <= '1';
wait for 5 ns;

--shift_to _right 
clk <= '0';
load <='0';
left_right <= '0';
wait for 5 ns;

--put result to dout
clk <= '1';
wait for 5 ns;


assert (din/= "0100")
report("assert1 din/= 0100")
severity warning;


-----------------------------
--#####     pattern 5     #####
----------------------------
--set load ='1' , input din to shift_val
clk <= '0';
load <= '1';
din <= "0001";
wait for 5 ns;

--put shift_val to dout 
clk <= '1';
wait for 5 ns;

--shift_to _right 
clk <= '0';
load <='0';
left_right <= '1';
wait for 5 ns;

--put result to dout
clk <= '1';
wait for 5 ns;


assert (din/= "0010")
report("assert1 din/= 0010")
severity warning;



-----------------------------
--#####     pattern 6     #####
----------------------------
--set load ='1' , input din to shift_val
clk <= '0';
load <= '1';
din <= "0010";
wait for 5 ns;

--put shift_val to dout 
clk <= '1';
wait for 5 ns;

--shift_to _right 
clk <= '0';
load <='0';
left_right <= '1';
wait for 5 ns;

--put result to dout
clk <= '1';
wait for 5 ns;


assert (din/= "0100")
report("assert1 din/= 0100")
severity warning;


-----------------------------
--#####     pattern 7     #####
----------------------------
--set load ='1' , input din to shift_val
clk <= '0';
load <= '1';
din <= "0100";
wait for 5 ns;

--put shift_val to dout 
clk <= '1';
wait for 5 ns;

--shift_to _right 
clk <= '0';
load <='0';
left_right <= '0';
wait for 5 ns;

--put result to dout
clk <= '1';
wait for 5 ns;


assert (din/= "1000")
report("assert1 din/= 1000")
severity warning;

-----------------------------
--#####     pattern 8     #####
----------------------------
--set load ='1' , input din to shift_val
clk <= '0';
load <= '1';
din <= "1000";
wait for 5 ns;

--put shift_val to dout 
clk <= '1';
wait for 5 ns;

--shift_to _left 
clk <= '0';
load <='0';
left_right <= '1';
wait for 5 ns;

--put result to dout
clk <= '1';
wait for 5 ns;


assert (din/= "0000")
report("assert1 din/= 0000")
severity warning;
--wait for 100 ns;
assert false 
report "---end of simulation---"
severity error;

end process;
--	clk <= not clk after 5 ns;
end BENCH;