72_display_driver.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--                             _ _
--                              L   
---------------------------OO-------OO---------------------------------
--                                                                   --
-- DESCRIPTION : training files                                      --
-- Author      : Chen DongYing & Zhang DongXiao                      --
-- AFFILIATION : ASIC Research Center of B.I.T.                      --
-- DATE        : 1999.06 14-20                                       --
-- COPYRIGHT   : (c) 1999-2001, Mentor China                         --
--                              ASIC Research Center of B.I.T.       --
--                                                                   --
-- This source file may be used and distributed without restriction  --
-- provided that this copyright statement is not removed  from  the  --
-- file and that any derivative work contains this copyright notice. --
--                                                                   --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

------------------------
entity display_driver is
------------------------
port(alarm_time   :in  t_clock_time;
     current_time :in  t_clock_time;
     new_time     :in  t_clock_time;
     show_new_time:in  std_logic;
     show_a       :in  std_logic;
     sound_alarm  :out std_logic;
     display      :out t_display);
end display_driver;

architecture rtl of display_driver is
   signal display_time:t_clock_time;
begin
   --
   -- output controls  
   --
   ctrl:process(alarm_time,current_time,new_time,show_a,show_new_time)
   begin
      --set alarm sound enable or not
      sound_lp: for i in alarm_time'range loop
         if not(alarm_time(i) = current_time(i)) then
            sound_alarm <= '0';
            exit sound_lp;
         else   
            sound_alarm <= '1';
         end if;
      end loop sound_lp;
   
      -- select display time
      if show_new_time = '1' then
         display_time <= new_time;
      elsif show_a = '1' then
         display_time <= alarm_time;
      elsif show_a = '0' then
         display_time <= current_time;
      else
--	     display_time <= (2,4,0,0);
         assert false report "Uncertain display_driver control!"
         severity warning;
      end if;
   end process;
   --
   -- seven segment display
   --
   disp:process(display_time)
   begin
--     if display_time(3)=2 and display_time(2)=4 then
--	     display <= ("UUUUUUU",
--		             "UUUUUUU",
--					 "UUUUUUU",
--					 "UUUUUUU");
--	  end if;
      for i in display_time'range loop
         display(i) <= seven_seg(display_time(i));
      end loop;
   end process;     
end rtl;