72_tb_display_driver.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

entity tb_display_driver is
end tb_display_driver;

architecture tb of tb_display_driver is
component display_driver
       port(alarm_time  :in t_clock_time;
            current_time:in t_clock_time;
            new_time     :in t_clock_time;
            show_new_time:in std_logic;
            show_a:in std_logic;
            sound_alarm:out std_logic;
            display:out t_display);
end component;
 
signal alarm_time:t_clock_time;
signal current_time:t_clock_time;
signal new_time:t_clock_time;
signal show_a:std_logic;
signal show_new_time:std_logic;
signal sound_alarm:std_logic;
signal display:t_display;

for all:display_driver use entity work.display_driver(rtl);
 
begin
    u1:display_driver
       port map(alarm_time,current_time,new_time,show_new_time,show_a,sound_alarm,display);

    process
    begin
    --initialize
    alarm_time <= (0,0,0,0);
    current_time <= (0,0,0,0);
    new_time <= (0,1,0,1);
    show_new_time <= '0';
    show_a <= '0';

    wait for 10 ns;
    --test vector1
    alarm_time <= (0,0,0,1);
    current_time <= (0,0,0,0);
    new_time <= (0,1,0,1);
    show_new_time <= '0';
    show_a <= '1'; 

    wait for 10 ns;
    --test vector2
    alarm_time <= (0,0,0,1);
    current_time <= (0,0,0,0);
    new_time <= (0,1,0,1);
    show_new_time <= '1';
    show_a <= '0'; 

    wait for 10 ns;
    --test vector3
    alarm_time <= (0,0,0,6);
    current_time <= (0,0,0,6);
    new_time <= (0,7,3,1);
    show_new_time <= '1';
    show_a <= '1'; 

    wait for 10 ns;
    --test vector4
    alarm_time <= (0,0,5,1);
    current_time <= (0,0,5,0);
    new_time <= (0,1,0,1);
    show_new_time <= '0';
    show_a <= 'X'; 

    wait for 10 ns;
    assert false report "End of Simulatin!"
    severity error;
    end process;
end tb;