📄 69_p_alarm_clock.vhd
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-- _ _
-- L
---------------------------OO-------OO---------------------------------
-- --
-- DESCRIPTION : training files --
-- Author : Chen DongYing & Zhang DongXiao --
-- AFFILIATION : ASIC Research Center of B.I.T. --
-- DATE : 1999.06 14-20 --
-- COPYRIGHT : (c) 1999-2001, Mentor China --
-- ASIC Research Center of B.I.T. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the --
-- file and that any derivative work contains this copyright notice. --
-- --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------
package p_alarm is
------------------
subtype t_digital is integer range 0 to 9;
subtype t_short is integer range 0 to 65535;
type t_clock_time is array (3 downto 0) of t_digital;
type t_display is array (3 downto 0) of std_logic_vector(6 downto 0);
type SEG7 is array (0 to 9) of std_logic_vector(6 downto 0);
constant seven_seg: SEG7 := (
"0111111",
"0000110",
"1011011",
"1001111",
"1100110",
"1101101",
"1111101",
"0000111",
"1111111",
"1110011"
);
type keypad9 is array (0 to 9) of std_logic_vector(9 downto 0);
constant keynumber: keypad9 := (
"0000000001", -- 0
"0000000010", -- 1
"0000000100", -- 2
"0000001000", -- 3
"0000010000", -- 4
"0000100000", -- 5
"0001000000", -- 6
"0010000000", -- 7
"0100000000", -- 8
"1000000000" -- 9
);
end p_alarm;
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