6_reg.vhd

来自「北京里工大学ASIC设计研究所的100个 VHDL程序设计例子」· VHDL 代码 · 共 20 行

entity bit_rtl_reg_clk is
   port ( 
	  pin  : bit_vector;
	  cntl : bit;
	  clk  : bit;
	  pout : out bit_vector
   );
end bit_rtl_reg_clk;

architecture func of bit_rtl_reg_clk is
begin
   process
   begin
	  wait until clk'event and clk ='1';
	  if (cntl = '1') then
		 pout <= pin ;
      end if;
   end process;
end func;