34_readwrite_stim.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--write by diao lan song
--1998/9/23

Use work.p.all;
    
ENTITY e_stim IS  END  e_stim ; 

ARCHITECTURE  stimulation OF e_stim IS 

COMPONENT e_bus
port(bus1  : Inout wired_and my_integer;
            bus_ready : In Bit);
END COMPONENT;
                            
    SIGNAL  bus1  :  wired_and my_integer;           
    SIGNAL  bus_ready   :  Bit;
    SIGNAL  clk   :  Bit;                         
BEGIN
  comp1 : e_bus  PORT MAP (bus1,bus_ready);

  e_stim: PROCESS

  BEGIN

    bus1   <= 3;
    bus_ready   <= '0';
    WAIT UNTIL clk = '1';

    bus_ready   <= '1';
    WAIT UNTIL clk = '1';

    bus1   <= 7;
    bus_ready   <= '0';
    WAIT UNTIL clk = '1';

    bus_ready   <= '1';
    WAIT UNTIL clk = '1';

    bus1   <= 5;
    bus_ready   <= '0';
    WAIT UNTIL clk = '1';

    bus_ready   <= '1';
    WAIT UNTIL clk = '1';

    bus1   <= 8;
    bus_ready   <= '0';
    WAIT UNTIL clk = '1';
 
    bus_ready   <= '1';
    WAIT UNTIL clk = '1';

    bus1   <= 9;
    bus_ready   <= '0';
    WAIT UNTIL clk = '1';

    bus_ready   <= '1';
    WAIT UNTIL clk = '1';

    bus1   <= 6;
    bus_ready   <= '0';
    WAIT UNTIL clk = '1';

    bus_ready   <= '1';
    WAIT UNTIL clk = '1';

    bus1   <= 4;
    bus_ready   <= '0';
    WAIT UNTIL clk = '1';

    bus_ready   <= '1';
    WAIT UNTIL clk = '1';

    bus1   <= 2;
loop1:for num in 0 to  18 loop
    bus_ready   <= '0';
    WAIT UNTIL clk = '1';

    bus_ready   <= '1';
    WAIT UNTIL clk = '1';
    end loop loop1;

    ASSERT false REPORT "End of Simulation" SEVERITY error;
 
  END PROCESS;


  e_clk: PROCESS

  BEGIN
    clk   <= '1';

    WHILE TRUE LOOP
        clk <= '0';
        WAIT FOR 10 ns;
        clk <= '1';                
        WAIT FOR 10 ns;
    END LOOP;
  END PROCESS;

END stimulation;   
         

configuration e_stim_conf of  e_stim is  
  for stimulation
    for comp1 : e_bus use entity work.e(arch);
    end for;  
  end for;  
end e_stim_conf;