61_assign.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--***************************************************************
--     Following first two examples show that object of std_logic and 
-- object of logic can be assigned to each other
--    Bbut object of std_logic_vector and objict of logic_vector
-- CAN'T be assigned to each other,they must be assigned to
-- each other by loop assignnment of signal objict,shows in 
-- example3 and example4
-- 1997.12.18
--*****************************************************************


-------------------------------------------------------------
--(1)following example shows that object of std_logic can be
--assigned to that  of logic
------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
--library dsp_lib;
use work.logic_pack.all;

entity tt1 is
  port(i : std_logic;
	   o  : out logic
      );
end tt1;

architecture ss of tt1 is
begin 
   o <= i;
end ss;
-------------------------------------------------------------
--(2)following example shows that object of std_logic can be 
--assigned to that  of logic
------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
--library dsp_lib;
use work.logic_pack.all;

entity tt2 is
  port(i : logic;
	   o  : out std_logic
      );
end tt2;

architecture ss of tt2 is
begin 
   o <= i;
end ss;
-------------------------------------------------------------
--(3)following example shows how an object of std_logic_vector 
-- can be assigned to that  of logic_vector
------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
--library dsp_lib;
use work.logic_pack.all;

entity tt3 is
  port(i1  : std_logic_vector(3 downto 0);
	   o  : out logic_vector(3 downto 0)
      );
end tt3;

architecture ss of tt3 is
begin 
  process(i1)
   begin
	 for I in 4 downto 0 loop
      o(I) <= i1(I);
     end loop;
  end process;
end ss;
-------------------------------------------------------------
--(4)following example shows how an object of std_logic_vector 
-- can be assigned by that  of logic_vector
------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
--library dsp_lib;
use work.logic_pack.all;

entity tt4 is
  port(i1 : logic_vector(3 downto 0);
	   o  : out std_logic_vector(3 downto 0)
      );
end tt4;

architecture ss of tt4 is
begin 
  process(i1)
   begin
	 for I in 4 downto 0 loop
      o(I) <= i1(I);
     end loop;
  end process;
end ss;