4_comp.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

entity bit_rtl_lt_nc is
   port ( 
	  in1  : bit_vector;
	  in2  : bit_vector;
	  pout : out bit
   );
end bit_rtl_lt_nc;

architecture func of bit_rtl_lt_nc is
begin
   process(in1,in2)
	  variable left : integer;
	  variable right: integer;
   begin
	  left  := bit_to_int(in1);
	  right := bit_to_int(in2);
	  if ( left < right ) then
		 pout <= '1' after 1 ns;
      else
		 pout <= '0' after 1 ns;
      end if;
   end process;
end  func;