73_tb_fq_divider.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library ieee;
use ieee.std_logic_1164.all;

entity tb_fq_divider is
end tb_fq_divider;

architecture test of tb_fq_divider is
component fq_divider       
       port(
            clk_in     :in  std_logic;
            reset      :in  std_logic;
            clk_out    :out std_logic);
end component;

signal clk_in    :std_logic;
signal reset     :std_logic;
signal clk_out   :std_logic;

for all:fq_divider use entity work.fq_divider(rtl);

begin
u1:fq_divider
   port map(clk_in,reset,clk_out);

clk_gen:process
  begin
  reset <= '1';
  wait for 2 ms;
  reset <= '0';
  clk_in <= '0';
  while true loop
      wait for 5 ms;
      clk_in <= not clk_in;
  end loop;
  end process;
end test;