73_fq_divider.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--                             _ _
--                              L   
---------------------------OO-------OO---------------------------------
--                                                                   --
-- DESCRIPTION : training files                                      --
-- Author      : Chen DongYing & Zhang DongXiao                      --
-- AFFILIATION : ASIC Research Center of B.I.T.                      --
-- DATE        : 1999.06 14-20                                       --
-- COPYRIGHT   : (c) 1999-2001, Mentor China                         --
--                              ASIC Research Center of B.I.T.       --
--                                                                   --
-- This source file may be used and distributed without restriction  --
-- provided that this copyright statement is not removed  from  the  --
-- file and that any derivative work contains this copyright notice. --
--                                                                   --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity fq_divider is
   port(
        clk_in      :in  std_logic;
        reset       :in  std_logic;
        clk_out     :out std_logic
        );
end fq_divider;

architecture rtl of fq_divider is
   constant divide_period : t_short := 6000;
begin
   divide_clk: process(clk_in,reset)
      variable cnt : t_short;
   begin
	  if (reset = '1') then
		 cnt           := 0;
		 clk_out <= '0';
	  elsif rising_edge(clk_in) then
		 if (cnt < (divide_period/2)) then
			clk_out <= '1';
		    cnt := cnt + 1;
         elsif (cnt < (divide_period-1)) then
			clk_out <= '0';
			cnt := cnt + 1;
	     else
			cnt := 0;
         end if;
      end if;
   end process; -- divide clk
end rtl;