21_test_13a.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--Page      : 283

--Objective : Deadlock

--Filename  : test_13a

--Author    : Joseph Pick

entity Test_13a is
end Test_13a;

architecture Behave_1 of Test_13a is
  
  signal A : NATURAL := 1;
  signal B : NATURAL := 1;

begin  

  Inc_A:
  process 
  begin
	wait on B;
	A <=A+1;
	assert FALSE
	  report "Simulation time has processed : Inc_A"
	  severity NOTE;
  end process Inc_A;

  Inc_B:
  process
  begin 
	wait on A;
	B <=B+1;
	assert FALSE
	  report "Simulation time has processed : Inc_B"
	  severity NOTE;
  end process Inc_B;
end Behave_1;