48_test_18e.vhd

来自「北京里工大学ASIC设计研究所的100个 VHDL程序设计例子」· VHDL 代码 · 共 39 行

entity Test_18e is

end Test_18e;

architecture Behave_1 of Test_18e is
  signal A : BIT := '0';
  signal B : BIT := '0';
  signal C : BIT := '0';
begin 
 
  Gen_Wave:
  process
  begin
	A <= '1' after 5 ns,
		  '0' after 9 ns;
	B <= '1' after 8 ns,
		 '0' after 14 ns;
	wait on A,B;
  end process Gen_Wave;

  Analysis_C:
  process
	variable Var_C : BIT := '0';
  begin 
    wait on C'TRANSACTION;
    Var_C := C;
  end  process Analysis_C;

  Update_C:C <= (A or B) after 40 ns;

  Finish:
  process
  begin 
  wait for 100 ns;
  assert false report "End of Simulation" severity error;
  end process Finish;

end Behave_1;