19_test_194.vhd

来自「北京里工大学ASIC设计研究所的100个 VHDL程序设计例子」· VHDL 代码 · 共 37 行

-- Page		 	: 345 -346
--
-- Objective 	: constancy of for loop bounds
--
-- File Name 	: test_194.vhd
--
-- Author    	: Joseph Pick
--


entity Test_194 is
end Test_194;

architecture Behave_1 of Test_194 is
begin

	process
		variable Lower : Natural := 5;
		variable Upper  : Natural := 10;
		variable Count	: Natural := 0;
	begin

		for I in Lower to Upper loop
			Count := Count + I;
			Lower := Lower + 1;
			Upper := Upper - 1;
		end loop;

		wait for 50 ns;
	end process;

end Behave_1;