2_adder.vhd

来自「北京里工大学ASIC设计研究所的100个 VHDL程序设计例子」· VHDL 代码 · 共 16 行

entity adder is
   port ( 
	  in1  : bit_vector;
	  in2  : bit_vector;
	  pout : out bit_vector
   );
end adder;  

architecture func of adder is
begin
   process(in1,in2)
   begin
	  pout <= in1+in2 after 2 ns;
   end process;
end  func;