66_pack.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.SIGNED_ARITH.all;
package coeffs is
  type coef_arr is array (0 to 16) of signed (8 downto 0);

  constant coefs: coef_arr:=(
   "111111001", "111111011", "000001101", "000010000",
   "111101101", "111010110", "000010111", "010011010",
   "011011110", "010011010", "000010111", "111010110",
   "111101101", "000010000", "000001101", "111111011", 
   "111111001");
end coeffs;