24_test_195.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Page		 	: 346 - 348
--
-- Objective 	: dangers of the artificial usage of inout ports
--
-- File Name 	: test_195.vhd
--
-- Author    	: Joseph Pick
--


entity Component_Test_195 is
	port (Clock : inout BIT);
end Component_Test_195;

architecture Behave_1 of Component_Test_195 is
begin
	Gen_Waveform:
	process
	begin
		wait for 50 ns;
		Clock <= not Clock;
	end process;
end Behave_1;

entity Test_195 is 
end Test_195;

architecture Behave_1 of Test_195 is
	component Component_Test_195 
		port (Clock : inout BIT);
	end component;

	function Or_Pull_Down (V : BIT_VECTOR ) return BIT is
		variable Result : BIT := '0';
	begin
		for I in V'RANGE loop
			if V(I) = '1' then
				Result := '1';
			end if;
		end loop;
		return Result;
	end Or_Pull_Down;

	signal Clock_Signal_A : Or_Pull_Down BIT;
	signal Clock_Signal_B : BIT;
		
for all:Component_Test_195 use entity work.Component_Test_195(Behave_1);
begin
	
	Instance_A: Component_Test_195
				port map (Clock => Clock_Signal_A);

	Instance_B: Component_Test_195
				port map (Clock => Clock_Signal_B);
	Waveform: Clock_Signal_A <= '0' after 75 ns,
                 			   '1' after 125 ns;
    Finish:
	process
	begin
    wait for 200 ns;
    assert false
      report "------End of Simulation------"
    severity error;
	end process Finish;

	Monitor_Clock_Signal_A:
	process
		variable Clock_Var_A : BIT;
	begin
		wait on Clock_Signal_A'TRANSACTION;
		Clock_Var_A := Clock_Signal_A;
	end process Monitor_Clock_Signal_A;

	Monitor_Clock_Signal_B:
	process
		variable Clock_Var_B: BIT;
	begin
		wait on Clock_Signal_B'TRANSACTION;
		Clock_Var_B := Clock_Signal_B;
	end process Monitor_Clock_Signal_B;

end Behave_1;