76_pid_stim.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library work;

entity test_pid is
end test_pid;

architecture beh of test_pid is
  component fu_pid
  port
   (	reset       : in bit;
	Fsignin     : in bit;
	HostInterrupt : in bit;
	PositionChange: in bit;
	Irefkout      : out real);
   end component;

   signal sig_rst,sig_Fin,sig_HI,sig_PC :bit;
   signal sig_Io : real;
   for all: fu_pid use entity work.pid(behavior);
 begin
  Inst_pid : fu_pid
  port map(
		   reset    =>sig_rst,
		   Fsignin  =>sig_Fin,
		   HostInterrupt =>sig_HI,
		   PositionChange=>sig_PC,
		   Irefkout      =>sig_Io);
  process
   begin
	sig_Fin<= '0';
	sig_HI <= '1';
	sig_PC <= '0';
	wait for 100 ns;
	sig_HI<= '0';
	wait for 100 ns;
	sig_PC <= '1';
	wait for 3500 ns; 

	sig_Fin<= '0';
	sig_HI <= '0';
	sig_PC <= '0';
	wait for 100 ns;
	sig_HI <= '0';
	wait for 100 ns;
	sig_PC <= '1';
	sig_HI <= '1';
	wait for 3500 ns;

	sig_Fin <= '1';
	sig_HI  <= '0';
	sig_PC  <= '0';
	wait for 100 ns;
	sig_HI  <= '0';
	wait for 100 ns;
	sig_PC <= '1';
	wait for 3500 ns;

	sig_Fin <= '1';
	sig_PC<= '0';
	wait for 100 ns;
	sig_HI<= '0';
	wait for 100 ns;
	sig_PC <= '1';
	sig_HI <= '1';
	wait for 6000 ns;

	assert false
	report "---End of Simulating---"
	severity error;
  end process;
end beh;