76_fpu.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

package op_pkg is 
  subtype int3bit is integer range 0 to 7;
end op_pkg;

package synchro is 
  FUnction rising_edge(signal sig:bit) return boolean;
end synchro;

package body synchro is 
  function rising_edge(signal sig:bit) return boolean is
  begin
	return (sig'event and sig='1' and sig'last_value = '0');
  end rising_edge;
end synchro;


use work.op_pkg.all;
use work.synchro.all;
entity fixedpointunit is
port
 (clock      : in bit;
  reset      : in bit;
  input1     : in real;
  input2     : in real;
  sel        : in bit;
  com        : in int3bit;
  output     : out real;
  outdone    : out bit);
end fixedpointunit;
architecture behavior of fixedpointunit is
begin
  process
	variable tmp: real;
	variable in1,in2:real;
	procedure mul(A,B : in real) is
	begin
	 tmp := A * B;
	end mul;
	procedure rep(A: in real) is
	begin
	  tmp := 1.0/A;
	end rep;
  begin
    wait until clock'event and clock = '1' and sel = '1';
	case com is 
	  when 1 => outdone <= '0'; 
				in1 := input1; 
				wait until rising_edge(clock);
				rep(in1);
				wait until rising_edge(clock);
				output <= tmp; outdone <= '1';
	  when 2 => outdone <= '0'; 
				in1 := input1; 
				in2 := input2; 
				wait until rising_edge(clock);
				mul(in1,in2);
				wait until rising_edge(clock);
				output <= tmp; outdone <= '1';
	  when 3 => output <= input1 + input2;
				wait until rising_edge(clock);
				outdone <= '1';
	  when 4 => output <= input1- input2;
				wait until rising_edge(clock);
				outdone <= '1';
	  when 5 => output <= tmp; outdone <= '1';
	  when others => outdone <= '1';
    end case;
  end process;
end behavior;