75_ram.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library ieee;
use ieee.std_logic_1164.all;
--library bitlib;
use work.bit_pack.all;

entity static_ram is
generic (  --下面给出的是RAM6116的时间特性值
           --在本系统的组装中将被置为43258A-25CMOS RAM
           --的时间特性值 
           constant taa  :time := 120 ns;
           constant tacs :time := 120 ns;
           constant tclz :time := 10 ns;
           constant tchz :time := 10 ns;
           constant toh  :time := 10 ns;
           constant twc  :time := 120 ns;
           constant taw  :time := 105 ns;
           constant twp  :time := 70 ns;
           constant twhz  :time := 35 ns; 
           constant tdw  :time := 35 ns; 
           constant tdh  :time := 0 ns; 
           constant tow  :time := 10 ns
         );
port (cs_b,we_b,oe_b :in bit;
      address :in bit_vector(7 downto 0);
      data :inout std_logic_vector(7 downto 0) := (others =>'Z')
      ); 
end static_ram;

architecture sram of static_ram is
type ramtype is array(0 to 255) of bit_vector(7 downto 0);
signal ram1:ramtype;-- := (others =>(others =>0));
signal flag:bit:='1';  
begin
 ram :process
 begin
    --使用flag信号值对ram1清零，且只进行一次
    if flag='1' then
     for i in 255 downto 0 loop
	  ram1(i)<="00000000";
     end loop;
     flag<='0';
    end if ;
    
    if (we_b'event and we_b='1' and cs_b'delayed ='0') or 
     (cs_b'event and cs_b='1' and we_b'delayed ='0') then 
     --写操作
     ram1(vec2int(address'delayed)) <=to_bitvector(data'delayed);
     --写操作完成后将数据读出
     --data'delayed的值是data变为高前的值
     data <=transport data'delayed after tow;
    end if;
    --置RAM为写模式  
    if (we_b'event and we_b='0' and cs_b='0') then
      data <=transport "ZZZZZZZZ" after twhz;
    end if;
    if cs_b'event and oe_b ='0' then 
       --RAM未选中
       if cs_b ='1' then
         data <=transport "ZZZZZZZZ" after tchz;
       --读操作
       elsif we_b ='1' then
        data <=transport "XXXXXXXX" after tclz;
        data <=transport to_stdlogicvector(ram1(vec2int(address))) after tacs;
       end if;
    end if;
    --读操作
    if address'event and cs_b ='0' and oe_b='0' and we_b='1' then
      data <="XXXXXXXX" after toh;
      data <=transport to_stdlogicvector(ram1(vec2int(address))) after taa;
    end if;
    wait on cs_b,we_b,address;
 end process ram;
 
 check :process
 begin
  if cs_b'delayed='0' and now/=0 ns then
     if address'event then
        --假定trc=twc
        assert (address'delayed'stable(twc))
        report "address cycle time too short"
        severity warning;
     end if;
       
       if (we_b'event and we_b='1') then
        assert (address'delayed'stable(taw))
        report "address not valid long enough to end of write"
        severity warning;
        assert (address'delayed'stable(twp))
        report "write pluse too short"
        severity warning;
        assert (data'delayed'stable(tdw))
        report "data setup time too short"
        severity warning;
        assert (data'last_event>=tdh)
        report "address cycle time too short"
        severity warning;
      end if;
  end if;
  wait on we_b,address,cs_b;
 end process check;
end sram;