35_486_sys.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--本描述是将前述各部件组装成一个完整的系统
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity i486_bus_sys is
end i486_bus_sys;

architecture bus_sys_bhv of i486_bus_sys is

component i486_bus
   port(
        abus:out bit_vector(31 downto 0);
        dbus:inout std_logic_vector(31 downto 0);
        w_rb,ads_b:out bit;
        rdy_b,clk :in bit:='0';
        address,w_data:in bit_vector(31 downto 0):=(others=>'0');
        r_data:out bit_vector(31 downto 0);
        wr,br:in bit:='0';
        std,done:out bit);
end component;

component static_ram
   generic ( constant taa,tacs,tclz,tchz,toh,twc,taw,twp,twhz,tdw,tdh,tow:time);
   port (  cs_b,we_b,oe_b:in bit;
           address : in bit_vector(7 downto 0);
           data :inout std_logic_vector(7 downto 0));
end component;

component memory_control
   port(
        clk,w_rb,ads_b,cs1:in bit;
        rdy_b,we_b,cs_b:out bit);
end component;

component tester
   port(
        address,w_data:out bit_vector(31 downto 0);
        r_data:in bit_vector(31 downto 0);
        clk,wr,br:out bit;
        std,done:in bit);
end component;

constant decode_delay : time :=5 ns;
constant addr_decode :bit_vector(31 downto 8):=(others=>'0');
signal cs1:bit:='1';
signal address,w_data,r_data:bit_vector(31 downto 0);
signal clk,wr,br,std,done:bit;
signal w_rb,ads_b,rdy_b: bit;
signal abus:bit_vector(31 downto 0);
signal dbus:std_logic_vector(31 downto 0);
signal cs_b,we_b:bit;

--信号oe_b在系统中总设定为低
signal oe_b :bit :='0';
 
begin
 bus1:i486_bus port map( abus,dbus,w_rb,ads_b,rdy_b,clk,address,w_data,r_data,wr,br,std,done);

 control1:memory_control port map(clk,w_rb,ads_b,cs1,rdy_b,we_b,cs_b);

 ram32 : for i in 3 downto 0 generate
   ram :static_ram
        generic map (25 ns,25 ns,3 ns,3 ns, 3 ns,25 ns,15 ns,15 ns,10 ns,12 ns,0 ns,0 ns)
        port map (cs_b,we_b,oe_b,abus(7 downto 0),dbus(8*i+7 downto 8*i));
 end generate ram32;

test:tester port map (address,w_data,r_data,clk,wr,br,std,done);

--判断地址信号是否在0到32,768之间，因为RAM地址信号只有15位
cs1 <='1' after decode_delay when (abus(31 downto 0)=addr_decode)
   else '0' after decode_delay;
end bus_sys_bhv;

        --系统配置文件
	configuration conf of i486_bus_sys is
	for bus_sys_bhv
	for ram32 
		for ram : static_ram use entity work.static_ram(sram);
		end for;
	end for;

	for bus1 : i486_bus use entity work.i486_bus(simple_486_bus);
	end for;

	for control1 : memory_control use entity work.memory_control(behavel);
	end for;

	for test : tester use entity work.tester(test1);
	end for;
	end for;
   end conf;