mc8051_struct.vhd

一个8051的VHDL代码

--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.mc8051.symbol
--
-- Author       :   Michael Mayer ([e-mail]),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 13:36:51
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY mc8051 IS
   PORT( 
      ea_n : IN     std_logic ;
      rst : IN     std_logic ;
      xtal1 : IN     std_logic ;
      ale : OUT    std_logic ;
      psen_n : OUT    std_logic ;
      xtal2 : OUT    std_logic ;
      P0 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
      P1 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
      P2 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
      P3 : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END mc8051 ;
--
-- VHDL Architecture mc8051.mc8051.struct
--
-- Created:
--          by - mrmayer.UNKNOWN (eceultra3.ece.umr.edu)
--          at - 13:36:55 09/22/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.4 (Build 18)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

LIBRARY mc8051;

ARCHITECTURE struct OF mc8051 IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL ac : std_logic;
SIGNAL ac_out : std_logic;
SIGNAL acc : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL acknow : std_logic;
SIGNAL addr_gb : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL cmp_true : std_logic;
SIGNAL cy : std_logic;
SIGNAL cy_out : std_logic;
SIGNAL cycle_states : std_logic_vector( 3 DOWNTO 0 ) ;
SIGNAL data_gb : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL dec_rd_sp : std_logic;
SIGNAL dptr : std_logic_vector( 15 DOWNTO 0 ) ;
SIGNAL inc_wr_sp : std_logic;
SIGNAL indirect_sel : std_logic;
SIGNAL int_clk : std_logic;
SIGNAL int_rst : std_logic;
SIGNAL ir : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL last_cycle : std_logic;
SIGNAL latch_pins : std_logic;
SIGNAL new_ir : std_logic;
SIGNAL ov : std_logic;
SIGNAL ov_out : std_logic;
SIGNAL p0_addr : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL p0_ctrl : std_logic;
SIGNAL p2_addr : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL p2_ctrl : std_logic;
SIGNAL parity : std_logic;
SIGNAL pdat_loc : std_logic_vector( 15 DOWNTO 0 ) ;
SIGNAL pdata : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL rd_gb : std_logic;
SIGNAL rd_n : std_logic;
SIGNAL rd_n_ctrl : std_logic;
SIGNAL rd_pmem1 : std_logic;
SIGNAL rd_pmem2 : std_logic;
SIGNAL read_latch : std_logic;
SIGNAL rom_data : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL rom_rd_n : std_logic;
SIGNAL rs : std_logic_vector( 1 DOWNTO 0 ) ;
SIGNAL rxd : std_logic;
SIGNAL rxd_ctrl : std_logic;
SIGNAL txd : std_logic;
SIGNAL txd_ctrl : std_logic;
SIGNAL wr_acc : std_logic;
SIGNAL wr_gb : std_logic;
SIGNAL wr_n : std_logic;
SIGNAL wr_n_ctrl : std_logic;
SIGNAL wr_out : std_logic;

-- Component Declarations
COMPONENT acc_reg
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_acc : IN     std_logic;
      wr_gb : IN     std_logic;
      acc : OUT    std_logic_vector( 7 DOWNTO 0 );
      acknow : OUT    std_logic;
      parity : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT b_sfr
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT cpu_core
   PORT (
      ac : IN     std_logic;
      acc : IN     std_logic_vector( 7 DOWNTO 0 );
      acknow : IN     std_logic;
      cy : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      ir : IN     std_logic_vector( 7 DOWNTO 0 );
      new_ir : IN     std_logic;
      ov : IN     std_logic;
      rs : IN     std_logic_vector( 1 DOWNTO 0 );
      ac_out : OUT    std_logic;
      addr_gb : OUT    std_logic_vector( 7 DOWNTO 0 );
      cmp_true : OUT    std_logic;
      cy_out : OUT    std_logic;
      dec_rd_sp : OUT    std_logic;
      inc_wr_sp : OUT    std_logic;
      indirect_sel : OUT    std_logic;
      ov_out : OUT    std_logic;
      rd_gb : OUT    std_logic;
      rd_pmem1 : OUT    std_logic;
      rd_pmem2 : OUT    std_logic;
      read_latch : OUT    std_logic;
      wr_acc : OUT    std_logic;
      wr_gb : OUT    std_logic;
      wr_out : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT dptr_reg
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      dptr : OUT    std_logic_vector( 15 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT hi_dmem
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT inter_ctrl
   PORT (
      P0 : IN     std_logic_vector( 7 DOWNTO 0 );
      acknow : IN     std_logic;
      cycle_states : IN     std_logic_vector( 3 DOWNTO 0 );
      dptr : IN     std_logic_vector( 15 DOWNTO 0 );
      ea_n : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      ir : IN     std_logic_vector( 7 DOWNTO 0 );
      last_cycle : IN     std_logic;
      pdat_loc : IN     std_logic_vector( 15 DOWNTO 0 );
      rom_data : IN     std_logic_vector( 7 DOWNTO 0 );
      rs : IN     std_logic_vector( 1 DOWNTO 0 );
      addr_gb : OUT    std_logic_vector( 7 DOWNTO 0 );
      ale : OUT    std_logic;
      indirect_sel : OUT    std_logic;
      p0_addr : OUT    std_logic_vector( 7 DOWNTO 0 );
      p0_ctrl : OUT    std_logic;
      p2_addr : OUT    std_logic_vector( 7 DOWNTO 0 );
      p2_ctrl : OUT    std_logic;
      pdata : OUT    std_logic_vector( 7 DOWNTO 0 );
      psen_n : OUT    std_logic;
      rd_gb : OUT    std_logic;
      rd_n : OUT    std_logic;
      rd_n_ctrl : OUT    std_logic;
      rom_rd_n : OUT    std_logic;
      wr_gb : OUT    std_logic;
      wr_n : OUT    std_logic;
      wr_n_ctrl : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT lo_dmem
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT osc_sm
   PORT (
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      xtal1 : IN     std_logic;
      cycle_states : OUT    std_logic_vector( 3 DOWNTO 0 );
      xtal2 : OUT    std_logic
   );
END COMPONENT;

COMPONENT p0_drv
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      latch_pins : IN     std_logic;
      p0_addr : IN     std_logic_vector( 7 DOWNTO 0 );
      p0_ctrl : IN     std_logic;
      rd_gb : IN     std_logic;
      read_latch : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      P0 : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT p1_drv
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      latch_pins : IN     std_logic;
      rd_gb : IN     std_logic;
      read_latch : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      P1 : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT p2_drv
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      latch_pins : IN     std_logic;
      p2_addr : IN     std_logic_vector( 7 DOWNTO 0 );
      p2_ctrl : IN     std_logic;
      rd_gb : IN     std_logic;
      read_latch : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      P2 : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT p3_drv
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      latch_pins : IN     std_logic;
      rd_gb : IN     std_logic;
      rd_n : IN     std_logic;
      rd_n_ctrl : IN     std_logic;
      read_latch : IN     std_logic;
      rxd_ctrl : IN     std_logic;
      txd : IN     std_logic;
      txd_ctrl : IN     std_logic;
      wr_gb : IN     std_logic;
      wr_n : IN     std_logic;
      wr_n_ctrl : IN     std_logic;
      acknow : OUT    std_logic;
      rxd : OUT    std_logic;
      P3 : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT prog_rom
   PORT (
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      p0_addr : IN     std_logic_vector( 7 DOWNTO 0 );
      p2_addr : IN     std_logic_vector( 7 DOWNTO 0 );
      rom_rd_n : IN     std_logic;
      rom_data : OUT    std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT program_ctrl
   PORT (
      cmp_true : IN     std_logic;
      cycle_states : IN     std_logic_vector( 3 DOWNTO 0 );
      dptr : IN     std_logic_vector( 15 DOWNTO 0 );
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      pdata : IN     std_logic_vector( 7 DOWNTO 0 );
      rd_pmem1 : IN     std_logic;
      rd_pmem2 : IN     std_logic;
      addr_gb : OUT    std_logic_vector( 7 DOWNTO 0 );
      dec_rd_sp : OUT    std_logic;
      inc_wr_sp : OUT    std_logic;
      indirect_sel : OUT    std_logic;
      ir : OUT    std_logic_vector( 7 DOWNTO 0 );
      last_cycle : OUT    std_logic;
      new_ir : OUT    std_logic;
      pdat_loc : OUT    std_logic_vector( 15 DOWNTO 0 );
      rd_gb : OUT    std_logic;
      wr_gb : OUT    std_logic;
      acknow : INOUT  std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT psw
   PORT (
      ac_out : IN     std_logic;
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      cy_out : IN     std_logic;
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      ov_out : IN     std_logic;
      parity : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      wr_out : IN     std_logic;
      ac : OUT    std_logic;
      acknow : OUT    std_logic;
      cy : OUT    std_logic;