debug.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

  variable annul  : std_logic;
  variable i      : std_logic;
  variable simm : std_logic_vector(12 downto 0);

  variable disen      : boolean := true;

begin

  if disen then

    op    := insn.op(31 downto 30);
    op2   := insn.op(24 downto 22);

    op3   := insn.op(24 downto 19);
    cond  := insn.op(28 downto 25);
    annul := insn.op(29);
    rs1   := insn.op(18 downto 14);
    rs2   := insn.op(4 downto 0);
    rd    := insn.op(29 downto 25);
    i     := insn.op(13);
    simm  := insn.op(12 downto 0);

    case op is
    when CALL => 
      addr := insn.pc + (insn.op(29 downto 0) & "00");
      return(tost(insn.pc) & bb & "call" & bl2 & "0x" & tost(addr));
    when FMT2 =>
      case op2 is
      when UNIMP => return(tost(insn.pc) & bb & "unimp");
      when SETHI =>
	if rd = "00000" then
          return(tost(insn.pc) & bb & "nop");
	else
          return(tost(insn.pc) & bb & "sethi" & bl2 & "%hi(0x" &
		tost(insn.op(21 downto 0) & "0000000000") & "), " & regdec(rd));
	end if;
      when BICC => 
        addr(31 downto 24) := (others => '0');
        addr(1 downto 0) := (others => '0');
        addr(23 downto 2) := insn.op(21 downto 0);
        if addr(23) = '1' then
          addr(31 downto 24) := (others => '1');
        else
          addr(31 downto 24) := (others => '0');
        end if;
        addr := addr + insn.pc;
        if insn.op(29) = '1' then
          return(tost(insn.pc) & bb & 'b' & branchop(insn) & ",a" & bl2 & 
		"0x" & tost(addr));
        else
          return(tost(insn.pc) & bb & 'b' & branchop(insn) & bl2 & 
		"0x" & tost(addr));
	end if;
--      when FBFCC => fptrap := not sregs.ef;
--      when CBCCC => cptrap := '1';
      when others => return(tost(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
      end case;
    when FMT3 =>
      case op3 is
      when IAND => return(tost(insn.pc) & bb & "and" & bl2 & regres(insn,hex));
      when IADD => return(tost(insn.pc) & bb & "add" & bl2 & regres(insn,dec));
      when IOR  => 
	if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
	  return(tost(insn.pc) & bb & "clr" & bl2 & regdec(rd));
	elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
	  return(tost(insn.pc) & bb & "mov" & bl2 & regres(insn,hex));
	else
	  return(tost(insn.pc) & bb & "or " & bl2 & regres(insn,hex));
	end if;
      when IXOR => return(tost(insn.pc) & bb & "xor" & bl2 & regres(insn,hex));
      when ISUB => return(tost(insn.pc) & bb & "sub" & bl2 & regres(insn,dec));
      when ANDN => return(tost(insn.pc) & bb & "andn" & bl2 & regres(insn,hex));
      when ORN  => return(tost(insn.pc) & bb & "orn" & bl2 & regres(insn,hex));
      when IXNOR =>
	if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
	  return(tost(insn.pc) & bb & "not" & bl2 & regdec(rd));
	else
	  return(tost(insn.pc) & bb & "xnor" & bl2 & regdec(rd));
	end if;
      when ADDX => return(tost(insn.pc) & bb & "addx" & bl2 & regres(insn,dec));
      when SUBX => return(tost(insn.pc) & bb & "subx" & bl2 & regres(insn,dec));
      when ADDCC => return(tost(insn.pc) & bb & "addcc" & bl2 & regres(insn,dec));
      when ANDCC => return(tost(insn.pc) & bb & "andcc" & bl2 & regres(insn,hex));
      when ORCC => return(tost(insn.pc) & bb & "orcc" & bl2 & regres(insn,hex));
      when XORCC => return(tost(insn.pc) & bb & "xorcc" & bl2 & regres(insn,hex));
      when SUBCC => return(tost(insn.pc) & bb & "subcc" & bl2 & regres(insn,dec));
      when ANDNCC => return(tost(insn.pc) & bb & "andncc" & bl2 & regres(insn,hex));
      when ORNCC => return(tost(insn.pc) & bb & "orncc" & bl2 & regres(insn,hex));
      when XNORCC => return(tost(insn.pc) & bb & "xnorcc" & bl2 & regres(insn,hex));
      when ADDXCC => return(tost(insn.pc) & bb & "addxcc" & bl2 & regres(insn,hex));
      when UMUL   => return(tost(insn.pc) & bb & "umul" & bl2 & regres(insn,dec));
      when SMUL   => return(tost(insn.pc) & bb & "smul" & bl2 & regres(insn,dec));
      when UMULCC => return(tost(insn.pc) & bb & "umulcc" & bl2 & regres(insn,dec));
      when SMULCC => return(tost(insn.pc) & bb & "smulcc" & bl2 & regres(insn,dec));
      when SUBXCC => return(tost(insn.pc) & bb & "subxcc" & bl2 & regres(insn,dec));
      when UDIVCC => return(tost(insn.pc) & bb & "udivcc" & bl2 & regres(insn,dec));
      when SDIVCC => return(tost(insn.pc) & bb & "sdivcc" & bl2 & regres(insn,dec));
      when TADDCC => return(tost(insn.pc) & bb & "taddcc" & bl2 & regres(insn,dec));
      when TSUBCC => return(tost(insn.pc) & bb & "tsubcc" & bl2 & regres(insn,dec));
      when TADDCCTV => return(tost(insn.pc) & bb & "taddcctv" & bl2 & regres(insn,dec));
      when TSUBCCTV => return(tost(insn.pc) & bb & "tsubcctv" & bl2 & regres(insn,dec));
      when MULSCC => return(tost(insn.pc) & bb & "mulscc" & bl2 & regres(insn,dec));
      when ISLL => return(tost(insn.pc) & bb & "sll" & bl2 & regres(insn,dec));
      when ISRL => return(tost(insn.pc) & bb & "srl" & bl2 & regres(insn,dec));
      when ISRA => return(tost(insn.pc) & bb & "sra" & bl2 & regres(insn,dec));
      when RDY  => return(tost(insn.pc) & bb & "mov" & bl2 & "%y, " & regdec(rd));
      when RDPSR  => return(tost(insn.pc) & bb & "mov" & bl2 & "%psr, " & regdec(rd));
      when RDWIM  => return(tost(insn.pc) & bb & "mov" & bl2 & "%wim, " & regdec(rd));
      when RDTBR  => return(tost(insn.pc) & bb & "mov" & bl2 & "%tbr, " & regdec(rd));
      when WRY  =>
	if (rs1 = "00000") or (rs2 = "00000") then
	  return(tost(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
	else
	  return(tost(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
	end if;
      when WRPSR  =>
	if (rs1 = "00000") or (rs2 = "00000") then
	  return(tost(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
	else
	  return(tost(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
	end if;
      when WRWIM  =>
	if (rs1 = "00000") or (rs2 = "00000") then
	  return(tost(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
	else
	  return(tost(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
	end if;
      when WRTBR  =>
	if (rs1 = "00000") or (rs2 = "00000") then
	  return(tost(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
	else
	  return(tost(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
	end if;
      when JMPL => 
	if (rd = "00000") then
	  if (i = '1') and (simm = "0000000001000") then
	    if (rs1 = "11111") then
	      return(tost(insn.pc) & bb & "ret");
	    elsif (rs1 = "01111") then
	      return(tost(insn.pc) & bb & "retl");
	    else
	      return(tost(insn.pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
	    end if;
	  else
	    return(tost(insn.pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
	  end if;
	else
	  return(tost(insn.pc) & bb & "jmpl" & bl2 & regres(insn,dec));
	end if;
      when TICC => 
        return(tost(insn.pc) & bb & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
      when FLUSH => 
        return(tost(insn.pc) & bb & "flush" & bl2 & regimm(insn,hex,false));
      when RETT => 
        return(tost(insn.pc) & bb & "rett" & bl2 & regimm(insn,dec,false));
      when RESTORE => 
	if (rd = "00000") then
	  return(tost(insn.pc) & bb & "restore");
	else
	  return(tost(insn.pc) & bb & "restore" & bl2 & regres(insn,hex));
	end if;
      when SAVE => 
	if (rd = "00000") then
	  return(tost(insn.pc) & bb & "save");
	else
	  return(tost(insn.pc) & bb & "save" & bl2 & regres(insn,dec));
	end if;
      when others => return(tost(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
      end case;
    when LDST =>
      case op3 is
      when ST => 
	if rd = "00000" then
	  return(tost(insn.pc) & bb & "clr" & bl2 & stparc(insn, rd, dec));
	else
	  return(tost(insn.pc) & bb & "st" & bl2 & stpar(insn, rd, dec));
	end if;
      when STB => 
	if rd = "00000" then
	  return(tost(insn.pc) & bb & "clrb" & bl2 & stparc(insn, rd, dec));
	else
	  return(tost(insn.pc) & bb & "stb" & bl2 & stpar(insn, rd, dec));
	end if;
      when STH => 
	if rd = "00000" then
	  return(tost(insn.pc) & bb & "clrh" & bl2 & stparc(insn, rd, dec));
	else
	  return(tost(insn.pc) & bb & "sth" & bl2 & stpar(insn, rd, dec));
	end if;
      when ISTD => 
	return(tost(insn.pc) & bb & "std" & bl2 & stpar(insn, rd, dec));
      when STA => 
	return(tost(insn.pc) & bb & "sta" & bl2 & stpara(insn, rd, dec));
      when STBA => 
	return(tost(insn.pc) & bb & "stba" & bl2 & stpara(insn, rd, dec));
      when STHA => 
	return(tost(insn.pc) & bb & "stha" & bl2 & stpara(insn, rd, dec));
      when STDA => 
	return(tost(insn.pc) & bb & "stda" & bl2 & stpara(insn, rd, dec));
      when LD => 
	return(tost(insn.pc) & bb & "ld" & bl2 & ldpar(insn, rd, dec));
      when LDUB => 
	return(tost(insn.pc) & bb & "ldub" & bl2 & ldpar(insn, rd, dec));
      when LDUH => 
	return(tost(insn.pc) & bb & "lduh" & bl2 & ldpar(insn, rd, dec));
      when LDD => 
	return(tost(insn.pc) & bb & "ldd" & bl2 & ldpar(insn, rd, dec));
      when LDSB => 
	return(tost(insn.pc) & bb & "ldsb" & bl2 & ldpar(insn, rd, dec));
      when LDSH => 
	return(tost(insn.pc) & bb & "ldsh" & bl2 & ldpar(insn, rd, dec));
      when LDSTUB => 
	return(tost(insn.pc) & bb & "ldstub" & bl2 & ldpar(insn, rd, dec));
      when SWAP   => 
	return(tost(insn.pc) & bb & "swap" & bl2 & ldpar(insn, rd, dec));
      when LDA => 
	return(tost(insn.pc) & bb & "lda" & bl2 & ldpara(insn, rd, dec));
      when LDUBA => 
	return(tost(insn.pc) & bb & "lduba" & bl2 & ldpara(insn, rd, dec));
      when LDUHA => 
	return(tost(insn.pc) & bb & "lduha" & bl2 & ldpara(insn, rd, dec));
      when LDDA => 
	return(tost(insn.pc) & bb & "ldda" & bl2 & ldpara(insn, rd, dec));
      when LDSBA => 
	return(tost(insn.pc) & bb & "ldsba" & bl2 & ldpara(insn, rd, dec));
      when LDSHA => 
	return(tost(insn.pc) & bb & "ldsha" & bl2 & ldpara(insn, rd, dec));
      when LDSTUBA => 
	return(tost(insn.pc) & bb & "ldstuba" & bl2 & ldpara(insn, rd, dec));
      when SWAPA   => 
	return(tost(insn.pc) & bb & "swapa" & bl2 & ldpara(insn, rd, dec));

      when others => return(tost(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
      end case;
    when others => return(tost(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
    end case;

  end if;
end;

procedure trace(signal debug : in iu_debug_type) is
  variable insn    : debug_info;
begin
    if (debug.rst = '1') and debug.clk'event and (debug.clk = '1') and ((debug.holdn = '1') or GATEDCLK) then
      if (debug.wr.annul or not debug.wr.pv) = '0' then
        insn.op := debug.wr.inst;
        insn.pc := debug.wr.pc(31 downto 2) & "00";
        if debug.trap = '1' then
	  print (disas(insn) & "  (trapped, tt = 0x" & tost(debug.tt) & ")");
	else
	  print (disas(insn));
	end if;
      end if;
    end if;
end;

end debug;