memtest.c

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

#include "leon.h"
#include "test.h"

extern volatile int dexcn;
volatile int stest;
volatile int dtest;
volatile int xtest;
volatile long long ytest, ddtmp;
volatile int xarr[2];
volatile char *ztest;
volatile int *yptr;

dblerr(int *p)
{
	asm("
	set	0x80000000, %o1
	set	0x80, %o3
	st	%o3, [%o1 + 0x08]
	ld	[%o0], %o2
	xor	%o2, 3, %o2
	st	%o2, [%o0]
	st	%g0, [%o1 + 0x08]
	");
}

int
edac_test()
{
	int tmp,i;


	if (!(lr->memcfg2 & 0x40)) 
		return(0);	/* skip test if edac disabled */
	report(EDAC_TEST);
	dexcn = 0;
	lr->memstatus = 0;			/* initialise MSTAT */
	lr->cachectrl &= ~0x0c;		/* disable data cache */

	/* test single-bit errors in all positions */

	stest = dtest = xtest = 0; 
	dblerr((int *) &dtest); dblerr((int *) &xtest);
	lr->edacctrl = 0x80; tmp = stest; stest = 1;

	if ((stest != 0) || (lr->failaddr != (int) &stest) ||
	   (lr->memstatus != 0x1d8))
	{
		fail(1);
	}

	for (i=1;i<32;i++) { stest = 1 << i; if (stest != 0) break; }
	if ((i!=32) || (lr->failaddr != (int) &stest) || 
		(lr->memstatus != 0x3d8))
	{
		fail(2);
	}

	/* check that multiple error and lock is set, and FAR loaded */

	lr->edacctrl = 0x0; dexcn = 1; tmp = dtest;
	if ((lr->failaddr != (int) &dtest) || (lr->memstatus != 0x7d9) ||
		(dexcn != 0)) { fail(3); }

	/* clear memory status register and provoke double error */
	lr->memstatus = 0; dexcn = 1; tmp = xtest;
	if ((lr->failaddr != (int) &xtest) || (lr->memstatus != 0x5d9) ||
		(dexcn != 0)) fail(4);

	/* check that multiple error is set and FAR not changed */
	dexcn = 1; tmp = dtest;
	if ((lr->failaddr != (int) &xtest) || (lr->memstatus != 0x7d9) ||
		(dexcn != 0)) fail(5);

	/* check errors during byte write */
	ztest = (char *) &dtest;
	lr->memstatus = 0; dexcn = 1; ztest[0] = 4;
	if ((lr->failaddr != (int) &dtest) || (lr->memstatus != 0x5d9) ||
		(dexcn != 0)) fail(6);
	lr->memcfg2 &= ~0x40;	/* disable edac */
	if (dtest != 3) fail(7);/* check that write cycle was aborted */
	lr->memcfg2 |= 0x40;	/* enable edac */

	stest = 0; lr->failaddr = 0;
	ztest = (char *) &stest;
	lr->edacctrl = 0x80; stest = 1^stest; lr->edacctrl = 0;
	lr->memstatus = 0; ztest[2] = 5;
	if ((stest!=0x500) || (lr->failaddr != (int) &stest) || 
		(lr->memstatus != 0x1d8))
		fail(8);

	/* check load/store double exceptions */
	ytest = 0; lr->failaddr = 0; yptr = (int *) &ytest; dblerr((int *)yptr);
	lr->memstatus = 0; dexcn = 1; ddtmp = 0;
	ddtmp = ytest;	/* read exception on first word */
	if ((lr->failaddr != (int) &ytest) || (lr->memstatus != 0x5d9))
		fail(9);

	ytest = 0; lr->failaddr = 0; dblerr((int *)&yptr[1]);
	lr->memstatus = 0; dexcn = 1;
	ddtmp = ytest;	/* exception on second word */
	if ((lr->failaddr != (int) &yptr[1]) || (lr->memstatus != 0x5d9))
		fail(10);

	flush();
	lr->cachectrl |= 0x0f;        /* enable icache & dcache */


}
	

memtest()
{

	volatile int wtest;

/* test I/O bus exception */

	report(MEM_TEST);

	lr->memcfg1 |= (0x41 << 20); /* enable BRDY signal */
	dexcn = 1; lr->failaddr = 0; lr->memstatus = 0;
	inb(80,0); /* cause read exception */
	if ((lr->failaddr != (IOAREA + 80)) || (lr->memstatus != 0x1dd) ||
		(dexcn != 0)) { fail(1); }
	dexcn = 1; lr->failaddr = 0; lr->memstatus = 0;
	inb(72,0); /* cause read exception */
	if ((lr->failaddr != (IOAREA + 72)) || (lr->memstatus != 0x1dd) ||
		(dexcn != 0)) { fail(2); }
	dexcn = 1; lr->failaddr = 0; lr->memstatus = 0;
	outb(80,0); /* cause write exception */
	if ((lr->failaddr != (IOAREA + 80)) || (lr->memstatus != 0x15d) ||
		(dexcn != 0)) { fail(2); }
	dexcn = 1; lr->failaddr = 0; lr->memstatus = 0;
	outb(72,0); /* cause write exception */
	if ((lr->failaddr != (IOAREA + 72)) || (lr->memstatus != 0x15d) ||
		(dexcn != 0)) { fail(4); }

/* write protection test */

	lr->writeprot1 = 1;
	if (lr->writeprot1) {
		lr->cachectrl &= ~0x0c;		/* disable data cache */
		dexcn = 1; lr->failaddr = 0; lr->memstatus = 0;
		lr->writeprot1 = 0xc000ffff;
		wtest = 1;
		if ((lr->failaddr != (int) &wtest) || (lr->memstatus != 0x55c) ||
			(dexcn != 0)) { fail(5); }
		dexcn = 1; lr->failaddr = 0; lr->memstatus = 0;
		lr->writeprot2 = 0x8000ffff;
		wtest = 1;
		if (dexcn != 1) { fail(6); }
		lr->writeprot2 = 0;
		lr->writeprot1 = 0xc0017fff;
		wtest = 1;
		if (dexcn != 1) { fail(7); }
		lr->writeprot1 = 0;
		lr->writeprot2 = 0x80007fff;
		wtest = 1;
		lr->writeprot2 = 0;
		if ((lr->failaddr != (int) &wtest) || (lr->memstatus != 0x55c) ||
			(dexcn != 0)) { fail(8); }
		flush();
		lr->cachectrl |= 0x0f;        /* enable icache & dcache */

	}
}