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📄 ramlib_mg2.lib

📁 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码
💻 LIB
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 type (bus39) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 38;
   bit_width : 39 ; /* number of bused pins */
 }
 type (bus33) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 32;
   bit_width : 33 ; /* number of bused pins */
 }
 type (bus32) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 31;
   bit_width : 32 ; /* number of bused pins */
 }
 type (bus29) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 28;
   bit_width : 29 ; /* number of bused pins */
 }
 type (bus28) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 27;
   bit_width : 28 ; /* number of bused pins */
 }
 type (bus25) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 24;
   bit_width : 25 ; /* number of bused pins */
 }
 type (bus24) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 23;
   bit_width : 24 ; /* number of bused pins */
 }
 type (bus23) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 22;
   bit_width : 23 ; /* number of bused pins */
 }
 type (bus22) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 21;
   bit_width : 22 ; /* number of bused pins */
 }
 type (bus21) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 20;
   bit_width : 21 ; /* number of bused pins */
 }
 type (bus12) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 11;
   bit_width : 12 ; /* number of bused pins */
 }
 type (bus11) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 10;
   bit_width : 11 ; /* number of bused pins */
 }
 type (bus10) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 9;
   bit_width : 10 ; /* number of bused pins */
 }
 type (bus9) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 8;
   bit_width : 9 ; /* number of bused pins */
 }
 type (bus8) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 7;
   bit_width : 8 ; /* number of bused pins */
 }
 type (bus7) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 6;
   bit_width : 7 ; /* number of bused pins */
 }
 type (bus6) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 5;
   bit_width : 6 ; /* number of bused pins */
 }
 type (bus5) { /* bus name */
   base_type : array;
   data_type : bit;
   bit_from : 4;
   bit_width : 5 ; /* number of bused pins */
 }

lu_table_template(cell_template) {
  variable_1 : input_net_transition;
  variable_2 : total_output_net_capacitance;
  index_1 ("0.0, 1.5");
  index_2 ("0.0, 4.0");
}
/* Define one-dimensional lu_table of size 4 */
lu_table_template(tran_template) {
  variable_1 : total_output_net_capacitance;
  index_1 ("0.0, 0.5, 1.5, 2.0");
}

 cell(itag_gen) {
   area : 1.000;
   pin(Inclock) {
     direction : input;
     capacitance : 1.0;
     fanout_load : 1.0;
   }
   bus(Data) {
     bus_type : bus29;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   bus(Address) {
     bus_type : bus6;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   pin(WE) {
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   bus(Q) {
     bus_type : bus29;
     direction :  output;
     timing() {
        timing_type : rising_edge ;
        related_pin : Inclock;
	cell_rise(cell_template) { values("8.00, 8.25", "8.11, 8.28"); }
	rise_transition(tran_template) { values("8.01, 8.08, 8.15, 8.40"); }
	cell_fall(cell_template) { values("8.00, 8.33", "8.11, 8.38"); }
	fall_transition(tran_template) { values("8.01, 8.11, 8.18, 8.40"); }
     }
   }
}

 cell(dtag_gen) {
   area : 1.000;
   pin(Inclock) {
     direction : input;
     capacitance : 1.0;
     fanout_load : 1.0;
   }
   bus(Data) {
     bus_type : bus25;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   bus(Address) {
     bus_type : bus7;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   pin(WE) {
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   bus(Q) {
     bus_type : bus25;
     direction :  output;
     timing() {
        timing_type : rising_edge ;
        related_pin : Inclock;
	cell_rise(cell_template) { values("8.00, 8.25", "8.11, 8.28"); }
	rise_transition(tran_template) { values("8.01, 8.08, 8.15, 8.40"); }
	cell_fall(cell_template) { values("8.00, 8.33", "8.11, 8.38"); }
	fall_transition(tran_template) { values("8.01, 8.11, 8.18, 8.40"); }
     }
   }
}

 cell(idat_gen) {
   area : 1.000;
   pin(Inclock) {
     direction : input;
     capacitance : 1.0;
     fanout_load : 1.0;
   }
   bus(Data) {
     bus_type : bus33;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   bus(Address) {
     bus_type : bus9;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   pin(WE) {
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   bus(Q) {
     bus_type : bus33;
     direction :  output;
     timing() {
        timing_type : rising_edge ;
        related_pin : Inclock;
	cell_rise(cell_template) { values("8.00, 8.25", "8.11, 8.28"); }
	rise_transition(tran_template) { values("8.01, 8.08, 8.15, 8.40"); }
	cell_fall(cell_template) { values("8.00, 8.33", "8.11, 8.38"); }
	fall_transition(tran_template) { values("8.01, 8.11, 8.18, 8.40"); }
     }
   }
}

 cell(ddat_gen) {
   area : 1.000;
   pin(Inclock) {
     direction : input;
     capacitance : 1.0;
     fanout_load : 1.0;
   }
   bus(Data) {
     bus_type : bus33;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   bus(Address) {
     bus_type : bus9;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   pin(WE) {
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
     }
     timing() {
         timing_type : hold_rising;
         related_pin : Inclock;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
     }
   }
   bus(Q) {
     bus_type : bus33;
     direction :  output;
     timing() {
        timing_type : rising_edge ;
        related_pin : Inclock;
	cell_rise(cell_template) { values("8.00, 8.25", "8.11, 8.28"); }
	rise_transition(tran_template) { values("8.01, 8.08, 8.15, 8.40"); }
	cell_fall(cell_template) { values("8.00, 8.33", "8.11, 8.38"); }
	fall_transition(tran_template) { values("8.01, 8.11, 8.18, 8.40"); }
     }
   }
}

 cell(syn_dpram_ruwr) {
   area : 1.000;
   pin(WrClock) {
     direction : input;
     capacitance : 1.0;
     fanout_load : 1.0;
   }
   pin(WrClken) {
     direction : input;
     capacitance : 1.0;
     fanout_load : 1.0;
     timing() {
         timing_type : setup_rising;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
         related_pin : "WrClock";
     }
     timing() {
         timing_type : hold_rising;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
         related_pin : WrClock;
     }
   }
   bus(Data) {
     bus_type : bus32;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
         related_pin : WrClock;
     }
     timing() {
         timing_type : hold_rising;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
         related_pin : WrClock;
     }
   }
   bus(WrAddress) {
     bus_type : bus8;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
         related_pin : WrClock;
     }
     timing() {
         timing_type : hold_rising;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
         related_pin : WrClock;
     }
   }
   pin(WrEn) {
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
     timing() {
         timing_type : setup_rising;
	 rise_constraint(scalar) { values("1.50"); }
	 fall_constraint(scalar) { values("1.50"); }
         related_pin : "WrClock";
     }
     timing() {
         timing_type : hold_rising;
	 rise_constraint(scalar) { values("0.50"); }
	 fall_constraint(scalar) { values("0.50"); }
         related_pin : WrClock;
     }
   }
   bus(RdAddress) {
     bus_type : bus8;
     direction : input;
     capacitance : 1.0000;
     fanout_load : 1.0000;
   }
   pin(RdEn) {
     direction : input;
     capacitance : 1.0;
     fanout_load : 1.0;
   }
   bus(Q) {
     bus_type : bus32;
     direction :  output;
     timing() {
        timing_type : combinational ;
	cell_rise(cell_template) { values("8.00, 8.25", "8.11, 8.28"); }
	rise_transition(tran_template) { values("8.01, 8.08, 8.15, 8.40"); }
	cell_fall(cell_template) { values("8.00, 8.33", "8.11, 8.38"); }
	fall_transition(tran_template) { values("8.01, 8.11, 8.18, 8.40"); }
        related_pin : RdEn;
     }
     timing() {
        timing_type : combinational ;
	cell_rise(cell_template) { values("8.00, 8.25", "8.11, 8.28"); }
	rise_transition(tran_template) { values("8.01, 8.08, 8.15, 8.40"); }
	cell_fall(cell_template) { values("8.00, 8.33", "8.11, 8.38"); }
	fall_transition(tran_template) { values("8.01, 8.11, 8.18, 8.40"); }
        related_bus_pins : RdAddress;
     }
     timing() {
        timing_type : rising_edge ;
	cell_rise(cell_template) { values("8.00, 8.25", "8.11, 8.28"); }
	rise_transition(tran_template) { values("8.01, 8.08, 8.15, 8.40"); }
	cell_fall(cell_template) { values("8.00, 8.33", "8.11, 8.38"); }
	fall_transition(tran_template) { values("8.01, 8.11, 8.18, 8.40"); }
        related_pin : WrClock;
     }
   }
}

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