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<br><link REV="made" HREF="mailto:jgais@wd.estec.esa.nl"><img SRC="../images/ws.gif" ALT="Spacecraft control and data systems division" height=88 width=480>
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<h1>
LEON-1 VHDL model</h1>
<h2>
Background</h2>
The LEON core is a <a href="http://www.sparc.org/">SPARC</a> compatible
integer unit developed for future space missions. It has been implemented
as a highly configurable, synthesisable VHDL model. To promote the SPARC
standard and enable development of system-on-a-chip (SOC) devices using
SPARC cores, the <a href="http://www.esa.int/">European Space Agency</a>
is making the full source code freely available under the <a href="http://www.gnu.org/">GNU</a>
GPL license.
<p>The LEON-1 processor should be seen as a demonstrator of the LEON core.
As such, it implements a minimum of interfaces and functions. Once the
LEON core has been fully verified, a more complete processor (LEON-2) will
be developed with functions such as PCI interface, floating-point unit
and DRAM controller.
<h2>
Architecture</h2>
LEON-1 is a SPARC compatible processor targeted for embedded applications.
It features the following functions:
<ul>
<li>
LEON SPARC compatible integer unit</li>
<li>
separate instruction and data caches</li>
<li>
32-bit memory bus with EDAC, PROM and SRAM support</li>
<li>
interrupt controller,</li>
<li>
two 24-bit timers</li>
<li>
two UARTs</li>
<li>
16-bit I/O port</li>
<li>
write protection</li>
<li>
power-down function</li>
<li>
watchdog.</li>
</ul>
<img SRC="leon.gif" height=461 width=511>
<br>
<br>
<h2>
Synthesis</h2>
The VHDL model is fully synthesisable and contains synthesis scripts for
<a href="http://www.synopsys.com/">Synopsys-DC</a>
and <a href="http://www.synplicity.com/">Synplify</a>. Targeting a 0.35
um CMOS process (gate-array or std-cell), approximately 100 MHz can be
reached with a gate count of 35 Kgates. The processor also fits in an <a href="http://www.altera.com/">Altera
10K200E FPGA</a>, utilising 65% of the device and running at 15 MHz.
<h2>
Simulation</h2>
The model comes with a generic testbench and test program, and includes
support files for the Modelsim simulator. It also features a built-in disassembler
for debug purposes.
<h2>
Software tools</h2>
Currently, software for LEON can be developed by reusing the <a href="http://www.estec.esa.nl/wsmwww/erc32/freesoft.html">ERC32CCS</a>
compiler for ERC32. However, no support exists for the LEON peripherals
(timers, UARTs) limiting the usability of the compiler. An adaptation of
ERC32CCS for LEON is in progress and will be made available in Q1 2000.
<h2>
Download</h2>
The LEON-1 VHDL model is provided under the <a href="COPYING">GNU GPL license</a>.
<ul>
<li>
<a href="leonspec.pdf">LEON-1 functional description</a></li>
<li>
L<a href="leonvhdl.pdf">EON-1 VHDL model description</a></li>
<li>
<a href="leon-1.0.tar.gz">LEON-1 VHDL model source code</a></li>
</ul>
Send comments, bug reports or enhancements to Jiri Gaisler (<a href="mailto:jgais@ws.estec.esa.nl">jgais@ws.estec.esa.nl</a>)
<br>
<p>
<hr><i>DISCLAIMER</i>
<p><i>All information is provided "as is", there is no warranty that the
information is correct or suitable for any purpose, neither implicit nor
explicit. This information does not necessarily reflect the policy of the
European Space Agency.</i>
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