cachemem.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	cachemem
-- File:	cachemem.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
-- Version control:
-- 17-02-1999:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;
use work.ramlib.all;

entity cachemem is
  port (
        clk   : in  std_logic;
	crami : in  cram_in_type;
	cramo : out cram_out_type
  );
end;

architecture rtl of cachemem is

  constant ITDEPTH : natural := 2**IOFFSET_BITS;
  constant ITWIDTH : natural := ITAG_BITS + ITPARBITS;
  constant DTDEPTH : natural := 2**DOFFSET_BITS;
  constant DTWIDTH : natural := DTAG_BITS + DTPARBITS;

  signal itaddr    : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
  signal idaddr    : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);

  signal itdatain  : std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
  signal itdataout : std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
  signal iddatain  : std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
  signal iddataout : std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
  signal itenable  : std_logic;
  signal idenable  : std_logic;
  signal itwrite   : std_logic;
  signal idwrite   : std_logic;

  signal dtaddr    : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
  signal ddaddr    : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
  signal dtdatain  : std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
  signal dtdataout : std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
  signal dddatain  : std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
  signal dddataout : std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
  signal dtenable  : std_logic;
  signal ddenable  : std_logic;
  signal dtwrite   : std_logic;
  signal ddwrite   : std_logic;

  signal vcc, gnd  : std_logic;

begin

  vcc <= '1'; gnd <= '0';
  itaddr <= crami.icramin.idramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
  idaddr <= crami.icramin.idramin.address;

  itinsel : process(crami)
  begin
    if ITAGPAR then
      itdatain(ITAG_BITS + ITPARBITS - 1) <= crami.icramin.itramin.parity;
    end if;
    itdatain(ITAG_BITS - 1 downto 0) <= crami.icramin.itramin.tag &
	    crami.icramin.itramin.valid;
    if IDATPAR then
      iddatain(IDWORD_BITS + IDPARBITS - 1) <= crami.icramin.idramin.parity;
    end if;
    iddatain(IDWORD_BITS - 1 downto 0) <= crami.icramin.idramin.data;

    if DTAGPAR then
      dtdatain(DTAG_BITS + DTPARBITS - 1) <= crami.dcramin.dtramin.parity;
    end if;
    dtdatain(DTAG_BITS - 1 downto 0) <= crami.dcramin.dtramin.tag &
	    crami.dcramin.dtramin.valid;
    if DDATPAR then
      dddatain(DDWORD_BITS + DDPARBITS - 1) <= crami.dcramin.ddramin.parity;
    end if;
    dddatain(DDWORD_BITS - 1 downto 0) <= crami.dcramin.ddramin.data;

  end process;

  itwrite   <= crami.icramin.itramin.write;
  idwrite   <= crami.icramin.idramin.write;
  itenable  <= crami.icramin.itramin.enable;
  idenable  <= crami.icramin.idramin.enable;

  dtaddr <= crami.dcramin.ddramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
  ddaddr <= crami.dcramin.ddramin.address;
  dtwrite   <= crami.dcramin.dtramin.write;
  ddwrite   <= crami.dcramin.ddramin.write;
  dtenable  <= crami.dcramin.dtramin.enable;
  ddenable  <= crami.dcramin.ddramin.enable;

  cramo.icramout.itramout.valid <= itdataout(ILINE_SIZE -1 downto 0);
  cramo.icramout.itramout.tag <= itdataout(ITAG_BITS-1 downto ILINE_SIZE);
  cramo.icramout.itramout.parity <= itdataout(ITAG_BITS -1 + ITPARBITS);
  cramo.icramout.idramout.data <= iddataout(IDWORD_BITS -1 downto 0);
  cramo.icramout.idramout.parity <= iddataout(IDWORD_BITS -1 + IDPARBITS);
  cramo.dcramout.dtramout.valid <= dtdataout(DLINE_SIZE -1 downto 0);
  cramo.dcramout.dtramout.tag <= dtdataout(DTAG_BITS-1 downto DLINE_SIZE);
  cramo.dcramout.dtramout.parity <= dtdataout(DTAG_BITS -1 + DTPARBITS);
  cramo.dcramout.ddramout.data <= dddataout(DDWORD_BITS -1 downto 0);
  cramo.dcramout.ddramout.parity <= dddataout(DDWORD_BITS -1 + DDPARBITS);

-- Icache tag memory

  behav : if TARGET_TECH = none generate 	-- Generic tag memory
    itags_none : syncram
      generic map ( width => ITAG_BITS+ITPARBITS, depth => IOFFSET_BITS)
      port map (
        address   => itaddr,
        clk       => clk,
        datain    => itdatain,
        dataout   => itdataout,
        enable    => itenable,
        write     => itwrite
      );

    dtags_none : syncram
      generic map ( width => DTAG_BITS+DTPARBITS, depth => DOFFSET_BITS)
      port map (
        address   => dtaddr,
        clk       => clk,
        datain    => dtdatain,
        dataout   => dtdataout,
        enable    => dtenable,
        write     => dtwrite
      );

    idata_none : syncram
      generic map ( width => IDWORD_BITS+IDPARBITS, depth => IOFFSET_BITS+ILINE_BITS)
      port map (
        address   => idaddr,
        clk       => clk,
        datain    => iddatain,
        dataout   => iddataout,
        enable    => idenable,
        write     => idwrite
      );

    ddata_none : syncram
      generic map ( width => DDWORD_BITS+DDPARBITS, depth => DOFFSET_BITS+DLINE_BITS)
      port map (
        address   => ddaddr,
        clk       => clk,
        datain    => dddatain,
        dataout   => dddataout,
        enable    => ddenable,
        write     => ddwrite
      );

  end generate;


  synpsyno : if (TARGET_TECH /= none) and 
	        ((SYNTOOL = synplify) or (SYNTOOL = synopsys)) generate

    itags : itag_synp
      port map (
        address   => itaddr,
        datain    => itdatain,
        clk	  => clk,
  	enable    => vcc,
        dataout   => itdataout,
        write     => itwrite
      );

    dtags : dtag_synp
      port map (
        address   => dtaddr,
        datain    => dtdatain,
        clk	  => clk,
  	enable    => vcc,
        dataout   => dtdataout,
        write     => dtwrite
      );

    idata : idat_synp
      port map (
        address   => idaddr,
        datain    => iddatain,
        clk	  => clk,
    	enable    => vcc,
        dataout   => iddataout,
        write     => idwrite
      );

    ddata : ddat_synp
      port map (
        address   => ddaddr,
        datain    => dddatain,
        clk	  => clk,
    	enable    => vcc,
        dataout   => dddataout,
        write     => ddwrite
      );

  end generate;

  exemplar : if SYNTOOL = leonardo generate	-- leonardo

    itags : syncramleo
    generic map (
      width => ITAG_BITS + ITPARBITS,
      depth => IOFFSET_BITS
    )
    port map (
      address   => itaddr,
      datain    => itdatain,
      clk       => clk,
      enable    => vcc,
      dataout   => itdataout,
      write     => itwrite
    );

    dtags : syncramleo
    generic map (
      width => DTAG_BITS + DTPARBITS,
      depth => DOFFSET_BITS
    )
    port map (
      address   => dtaddr,
      datain    => dtdatain,
      clk       => clk,
      enable    => vcc,
      dataout   => dtdataout,
      write     => dtwrite
    );

    idata : syncramleo
    generic map (
      width => IDWORD_BITS + IDPARBITS,
      depth => IOFFSET_BITS + ILINE_BITS
    )
    port map (
      address   => idaddr,
      datain    => iddatain,
      clk       => clk,
      enable    => vcc,
      dataout   => iddataout,
      write     => idwrite
    );

   ddata : syncramleo
   generic map (
     width => DDWORD_BITS + DDPARBITS,
     depth => DOFFSET_BITS +DLINE_BITS
   )
   port map (
     address   => ddaddr,
     datain    => dddatain,
     clk       => clk,
     enable    => vcc,
     dataout   => dddataout,
     write     => ddwrite
    );

  end generate;

end ;