peri.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	peri
-- File:	peri.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	This unit instantiates all peripherals
------------------------------------------------------------------------------
-- Version control:
-- 11-10-1998:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.iface.all;

entity peri is
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    pbo    : out pbus_out_type;
    pei    : in  peri_in_type;
    peo    : out peri_out_type
  );
end; 

architecture rtl of peri is

component irqctrl
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    pbo    : out pbus_out_type;
    irqi   : in  irq_in_type;
    irqo   : out irq_out_type
  );
end component;

component timers 
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    pbo    : out pbus_out_type;
    timo   : out timers_out_type
  );
end component;

component uart
  generic (id : integer range 0 to 3 := 0);
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    pbo    : out pbus_out_type;
    uarti  : in  uart_in_type;
    uarto  : out uart_out_type
  );
end component; 

component ioport
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    pbo    : out pbus_out_type;
    uart1o : in  uart_out_type;
    uart2o : in  uart_out_type;
    pei    : in  peri_in_type;
    pioo   : out pio_out_type
  );
end component;

signal irqi   : irq_in_type;
signal irqo   : irq_out_type;
signal timo   : timers_out_type;
signal pioo   : pio_out_type;
signal pbot, pbou1, pbou2, pboirq, pbop : pbus_out_type;
signal uart1i, uart2i  : uart_in_type;
signal uart1o, uart2o  : uart_out_type;

begin

-- UARTS
-- This stupidity exists because synopsys DC is not capable of
-- handling record elements in port maps. Sad really ...

  uart1i.rxd     <= pioo.rxd(0); uart1i.ctsn    <= pioo.ctsn(0);
  uart2i.rxd     <= pioo.rxd(1); uart2i.ctsn    <= pioo.ctsn(1);

  uart1    : uart 
  generic map(id => 0)
  port map ( rst => rst, clk => clk, pbi => pbi, pbo => pbou1,
      	     uarti => uart1i, uarto => uart1o);
      
  uart2    : uart 
  generic map(id => 1)
  port map ( rst => rst, clk => clk, pbi => pbi, pbo => pbou2,
             uarti => uart2i, uarto => uart2o);

-- interrupt controller

  irqi.intack  <= pei.intack; irqi.irl     <= pei.iv;

  irqctrl0 : irqctrl 
  port map ( rst  => rst, clk  => clk, pbi => pbi, pbo => pboirq,
      	     irqi => irqi, irqo => irqo);

-- timers (and watchdog)

  peo.wdog     <= timo.wdog;

  timers0 : timers 
  port map ( rst  => rst, clk  => clk, pbi => pbi, pbo => pbot, timo => timo);

-- parallel I/O port

  ioport0 : ioport 
  port map ( rst  => rst, clk  => clk, pbi => pbi, pbo => pbop,
             uart1o => uart1o, uart2o => uart2o, pei => pei, pioo => pioo);

-- IRQ assignment

  irqi.irq(15) <= '0';			     -- unused
  irqi.irq(14) <= '0';			     -- reserved for DMA
  irqi.irq(13 downto 10) <= (others => '0'); -- PCI interrupts should go here
  irqi.irq(9) <=  timo.irq(1);		     -- timer 2
  irqi.irq(8) <=  timo.irq(0);		     -- timer 1
  irqi.irq(7 downto 4) <= pioo.irq;	     -- I/O port interrupts
  irqi.irq(3)    <= uart1o.irq;		     -- UART 1
  irqi.irq(2)    <= uart2o.irq;		     -- UART 2
  irqi.irq(1) <= pei.cerror;		     -- EDAC correctable error

-- drive outputs

  peo.irl      <= irqo.irl;
  peo.piol     <= pioo.piol;
  peo.piodir   <= pioo.piodir;
  peo.romwidth <= pioo.romwidth;
  peo.romedac  <= pioo.romedac;

  pbo.data <= pbou1.data or pbou2.data or pbot.data or pboirq.data or pbop.data;

end;