config_altera.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	config
-- File:	config.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Altera specific LEON configuration package
------------------------------------------------------------------------------
-- Version control:
-- 17-02-1999:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

package config is

----------------------------------------------------------------------------
-- target technology and synthesis tools
----------------------------------------------------------------------------

type targettech is (none, altera, mg2, mietec);
constant TARGET_TECH	: targettech := altera;
type synthtool is (none, synplify, synopsys, leonardo);
constant SYNTOOL 	: synthtool := synplify;

----------------------------------------------------------------------------
-- select clocking strategy
----------------------------------------------------------------------------

constant GATEDCLK  : boolean := false;

----------------------------------------------------------------------------
-- processor configuration
----------------------------------------------------------------------------

constant IMPL : std_logic_vector(3 downto 0) := "0000";
constant VER  : std_logic_vector(3 downto 0) := "0000";
constant NWINDOWS  : integer := 8;	-- number of register windows (2 - 32)
constant NWINLOG2  : integer := 3;	-- log2(NWINDOWS) 
constant RABITS  : integer := 8;	-- log2(NWINDOWS+1) + 4
constant FPDIS : std_logic := '1';	-- FPU disabled 

-- instruction options

type multype is (none, iterative, hard32); -- none, slow iterative, hardware

constant MULTIPLIER : multype := none;

-- constants below are auto-generated, do not edit

constant CWPOPT : boolean := (NWINDOWS = (2**NWINLOG2));

----------------------------------------------------------------------------
-- instruction cache configuration
----------------------------------------------------------------------------

constant ITPARBITS    : natural := 0; -- number of tag parity bits (0/1)
constant ITAGAPAR     : std_logic := '0'; -- include address in tag parity
constant IDPARBITS    : natural := 0; -- number of data parity bits (0/1)
constant IDATAPAR     : std_logic := '0'; -- include address in data parity
constant ILINE_BITS   : integer := 3;	-- address bits per line
constant IOFFSET_BITS : integer := 6;	-- address bits in the offset
constant ITAG_HIGH    : integer := 30;	-- top address bit in cache

-- constants below are auto-generated, do not edit

constant ILINE_SIZE   : integer := 2**ILINE_BITS; -- instructions per line
constant ITAG_BITS    : integer := ITAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 +
				   ILINE_SIZE + 1;
constant ITAGPAR      : boolean := ITPARBITS /= 0; -- tag parity checking
constant IDATPAR      : boolean := IDPARBITS /= 0; -- data parity checking
constant IDWORD_BITS  : integer := 32;	-- data bits per word

----------------------------------------------------------------------------
-- data cache configuration
----------------------------------------------------------------------------

constant DTPARBITS    : natural := 0; -- number of tag parity bits (0/1)
constant DTAGAPAR     : std_logic := '0'; -- include address in tag parity
constant DDPARBITS    : natural := 0; -- number of data parity bits (0/1)
constant DDATAPAR     : std_logic := '0'; -- include address in data parity
constant DLINE_BITS   : integer := 2;	-- address bits per line
constant DOFFSET_BITS : integer := 7;	-- address bits in offset
constant DTAG_HIGH    : integer := 30;	-- top address bit in cache

-- constants below are auto-generated, do not edit

constant DLINE_SIZE   : integer := 2**DLINE_BITS; -- data words per line
constant DTAG_BITS    : integer := DTAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 +
				   DLINE_SIZE + 1;
constant DTAGPAR      : boolean := DTPARBITS /= 0; -- tag parity checking
constant DDATPAR      : boolean := DDPARBITS /= 0; -- data parity checking
constant DDWORD_BITS  : integer := 32;	-- data bits per word

----------------------------------------------------------------------------
-- Peripheral options
----------------------------------------------------------------------------

constant IOADDRMAX   : integer := 7;	-- top bit for I/O address decoding
constant TIMERSBITS  : integer := 24;	-- number of bits in timers
constant UART0ADDR   : std_logic_vector := "0111";   -- Uart 0 start address
constant UART1ADDR   : std_logic_vector := "1000";   -- Uart 1 start address
constant WPROTEN     : boolean := false;	-- enable write protection

----------------------------------------------------------------------------
-- memory interface options
----------------------------------------------------------------------------

constant MEMEDAC  : boolean := false;	-- memory EDAC
constant RAWADDR  : boolean := false;	-- unlatched address option
constant DMAEN    : std_logic := '0';	-- enable DMA interface

----------------------------------------------------------------------------
-- speed/area trade-offs
----------------------------------------------------------------------------

constant FASTJUMP  : boolean := false;	-- speeds up jump address generation
constant FASTEDAC  : boolean := false;	-- speeds up EDAC operation
constant LDDELAY   : integer range 1 to 2 := 2;	-- load delay cycles

----------------------------------------------------------------------------
-- debugging
----------------------------------------------------------------------------

constant DEBUGPORT : boolean := false;	-- enable iu debug port
constant PCLOW : integer := 2; 	-- set to 0 for simulation, 2 for synthesis
constant HALTONERROR : std_logic := '1'; -- set to '0' for test, otherwise '1'

end;