ramlib.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

  ddat_gen0 : ddat_gen
    port map (
      inclock       => clk,
      address   => address,
      data    => datain,
      q   => dataout,
      we     => write
    );

end arch0;

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity idat_synp  is
  port (
    address  : in std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
    dataout  : out std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic
  );
attribute syn_isclock : boolean;
attribute syn_isclock of clk : signal is true;
end;

architecture arch0 of idat_synp is

component idat_gen
  port (
    address  : in std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
    inclock      : in std_logic;
    data   : in std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
    q  : out std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
    we    : in std_logic
  );
end component;

attribute syn_white_box : boolean;
attribute syn_white_box of idat_gen : component is true;
--Estimated timing data for -3 speed grade
--Degradation factor ~ 1.25 to estimate timing for a -4 speed grade
attribute syn_scaletiming : string;
attribute syn_scaletiming of idat_gen : component is "eab_scale";
attribute syn_tsu1 : string;
attribute syn_tsu2 : string;
attribute syn_tsu3 : string;
attribute syn_tco1 : string;
attribute syn_tsu1 of idat_gen : component is "data[*]->inclock=5.3";
attribute syn_tsu2 of idat_gen : component is "address[*]->inclock=5.3";
attribute syn_tsu3 of idat_gen : component is "we->inclock=5.5";
attribute syn_tco1 of idat_gen : component is "inclock->q[*]=13.7";
attribute LPM_WIDTH : POSITIVE;
attribute LPM_WIDTH of idat_gen : component is IDWORD_BITS + IDPARBITS;
attribute LPM_TYPE : STRING;
attribute LPM_TYPE of idat_gen : component is "LPM_RAM_DQ";
attribute LPM_WIDTHAD : POSITIVE;
attribute LPM_WIDTHAD of idat_gen : component is IOFFSET_BITS + ILINE_BITS;
--attribute LPM_NUMWORDS : STRING;
--attribute LPM_NUMWORDS of idat_gen : component is LPM_NUMWORDS;
attribute LPM_FILE : STRING;
attribute LPM_FILE of idat_gen : component is "UNUSED";
attribute LPM_INDATA : STRING;
attribute LPM_INDATA of idat_gen : component is "REGISTERED";
attribute LPM_ADDRESS_CONTROL : STRING;
attribute LPM_ADDRESS_CONTROL of idat_gen : component is "REGISTERED";
attribute LPM_OUTDATA : STRING;
attribute LPM_OUTDATA of idat_gen : component is "UNREGISTERED";
attribute LPM_HINT : STRING;
attribute LPM_HINT of idat_gen : component is "USE_EAB";
attribute altera_area : integer;
attribute altera_area of idat_gen : component is 0;

signal vcc : std_logic;

begin
  vcc <= '1';
  idat_gen0 : idat_gen
    port map (
      inclock       => clk,
      address   => address,
      data    => datain,
      q   => dataout,
      we     => write
    );

end arch0;


library IEEE;
use IEEE.std_logic_1164.all;

entity syn_ram_256x22 is
     port ( data    : in std_logic_vector(21 downto 0);
            address : in std_logic_vector(7 downto 0);
            clk: in std_logic;
            clken: in std_logic;
            we : in std_logic;
            q : out std_logic_vector(21 downto 0)
     );
end;

architecture behavioral of syn_ram_256x22 is
-- pragma translate_off
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
-- pragma translate_on
begin
-- pragma translate_off
      dtags : syncram
        generic map ( width => 22, depth => 8)
        port map (
          clk       => clk,
          address   => address,
          datain    => data,
          dataout   => q,
          enable    => clken,
          write     => we
        );
-- pragma translate_on
end behavioral;

library IEEE;
use IEEE.std_logic_1164.all;

entity syn_ram_256x23 is
     port ( data    : in std_logic_vector(22 downto 0);
            address : in std_logic_vector(7 downto 0);
            clk: in std_logic;
            clken: in std_logic;
            we : in std_logic;
            q : out std_logic_vector(22 downto 0)
     );
end;

architecture behavioral of syn_ram_256x23 is
-- pragma translate_off
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
-- pragma translate_on
begin
-- pragma translate_off
      dtags : syncram
        generic map ( width => 23, depth => 8)
        port map (
          clk       => clk,
          address   => address,
          datain    => data,
          dataout   => q,
          enable    => clken,
          write     => we
        );
-- pragma translate_on
end behavioral;

library IEEE;
use IEEE.std_logic_1164.all;

entity syn_ram_256x24 is
     port ( data    : in std_logic_vector(23 downto 0);
            address : in std_logic_vector(7 downto 0);
            clk: in std_logic;
            clken: in std_logic;
            we : in std_logic;
            q : out std_logic_vector(23 downto 0)
     );
end;

architecture behavioral of syn_ram_256x24 is
-- pragma translate_off
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
-- pragma translate_on
begin
-- pragma translate_off
      dtags : syncram
        generic map ( width => 24, depth => 8)
        port map (
          clk       => clk,
          address   => address,
          datain    => data,
          dataout   => q,
          enable    => clken,
          write     => we
        );
-- pragma translate_on
end behavioral;

library IEEE;
use IEEE.std_logic_1164.all;

entity syn_ram_128x28 is
     port ( data    : in std_logic_vector(27 downto 0);
            address : in std_logic_vector(6 downto 0);
            clk: in std_logic;
            clken: in std_logic;
            we : in std_logic;
            q : out std_logic_vector(27 downto 0)
     );
end;

architecture behavioral of syn_ram_128x28 is
-- pragma translate_off
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
-- pragma translate_on
begin
-- pragma translate_off
      dtags : syncram
        generic map ( width => 28, depth => 7)
        port map (
          clk       => clk,
          address   => address,
          datain    => data,
          dataout   => q,
          enable    => clken,
          write     => we
        );
-- pragma translate_on
end behavioral;

-- ram package that declares all ram models

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;


package ramlib is

component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;

component syncramleo 
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    address  : in std_logic_vector((depth -1) downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
  ); 
end component;     

component regfile
  port (
    Clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;		
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end component;

component syn_ram_256x21
     port ( Data    : in std_logic_vector(20 downto 0);
            Address : in std_logic_vector(7 downto 0);
            Clk: in std_logic;
            Clken: in std_logic;
            WE : in std_logic;
            Q : out std_logic_vector(20 downto 0)
     );
end component;

component syn_ram_256x22
     port ( Data    : in std_logic_vector(21 downto 0);
            Address : in std_logic_vector(7 downto 0);
            Clk: in std_logic;
            Clken: in std_logic;
            WE : in std_logic;
            Q : out std_logic_vector(21 downto 0)
     );
end component;

component syn_ram_256x23
     port ( Data    : in std_logic_vector(22 downto 0);
            Address : in std_logic_vector(7 downto 0);
            Clk: in std_logic;
            Clken: in std_logic;
            WE : in std_logic;
            Q : out std_logic_vector(22 downto 0)
     );
end component;

component syn_ram_256x24
     port ( Data    : in std_logic_vector(23 downto 0);
            Address : in std_logic_vector(7 downto 0);
            Clk: in std_logic;
            Clken: in std_logic;
            WE : in std_logic;
            Q : out std_logic_vector(23 downto 0)
     );
end component;

component syn_ram_1024x32
     port ( Data    : in std_logic_vector(31 downto 0);
            Address : in std_logic_vector(9 downto 0);
            Clk: in std_logic;
            Clken: in std_logic;
            WE : in std_logic;
            Q : out std_logic_vector(31 downto 0)
     );
end component;

component syn_ram_1024x33
     port ( Data    : in std_logic_vector(32 downto 0);
            Address : in std_logic_vector(9 downto 0);
            Clk: in std_logic;
            Clken: in std_logic;
            WE : in std_logic;
            Q : out std_logic_vector(32 downto 0)
     );
end component;

component syn_ram_128x28
     port ( Data    : in std_logic_vector(27 downto 0);
            Address : in std_logic_vector(6 downto 0);
            Clk: in std_logic;
            Clken: in std_logic;
            WE : in std_logic;
            Q : out std_logic_vector(27 downto 0)
     );
end component;

component dtag_synp 
  port (
    address  : in std_logic_vector(DOFFSET_BITS -1 downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
    dataout  : out std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic
  );
end component;

component itag_synp 
  port (
    address  : in std_logic_vector(IOFFSET_BITS -1 downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
    dataout  : out std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic
  );
end component;

component idat_synp 
  port (
    address  : in std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
    dataout  : out std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic
  );
end component;
component ddat_synp 
  port (
    address  : in std_logic_vector(DOFFSET_BITS +DLINE_BITS -1 downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
    dataout  : out std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic
  );
end component;

component rfgen
  port (
    Clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end component;

component rfaltsynp
  port (
    Clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end component;

component rfaltsyno
  port (
    clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end component;

component rfaltleo
  port (
    clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end component;

end ramlib;