ramlib.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

      ra <= address;
      if write = '1' then
        memarr(conv_integer(unsigned(address))) <= datain;
      end if;
    end if;
    dataout <= memarr(conv_integer(unsigned(ra)));
  end process;

end;

-- cache rams for synopsys

library IEEE;
use IEEE.std_logic_1164.all;

entity syn_ram_256x21 is
     port ( data    : in std_logic_vector(20 downto 0);
            address : in std_logic_vector(7 downto 0);
            clk: in std_logic;
            clken: in std_logic;
            we : in std_logic;
            q : out std_logic_vector(20 downto 0)
     );
end;


architecture behavioral of syn_ram_256x21 is
-- pragma translate_off
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
-- pragma translate_on
begin
-- pragma translate_off
      dtags : syncram
        generic map ( width => 21, depth => 8)
        port map (
          clk       => clk,
          address   => address,
          datain    => data,
          dataout   => q,
          enable    => clken,
          write     => we
        );
-- pragma translate_on
end behavioral;

-- pragma translate_off
-- Dcache tag model for altera/synplify

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity dtag_gen is
  port (
    address  : in std_logic_vector(DOFFSET_BITS -1 downto 0);
    inclock      : in std_logic;
    data     : in std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
    q  : out std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
    we    : in std_logic
  );
end;

architecture behavioral of dtag_gen is
signal vcc : std_logic := '1';
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
begin
      syncram0 : syncram
        generic map ( depth => address'length, width => data'length)
        port map (
          clk       => inclock,
          address   => address,
          datain    => data,
          dataout   => q,
	  enable    => vcc,
          write     => we
        );
end behavioral;

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity itag_gen is
  port (
    address  : in std_logic_vector(IOFFSET_BITS -1 downto 0);
    inclock    : in std_logic;
    data   : in std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
    q  : out std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
    we    : in std_logic
  );
end;

architecture behavioral of itag_gen is
signal vcc : std_logic := '1';
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
begin
      synram0 : syncram
        generic map ( depth => address'length, width => data'length)
        port map (
          clk       => inclock,
          address   => address,
          datain    => data,
          dataout   => q,
	  enable    => vcc,
          write     => we
        );
end behavioral;

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity ddat_gen is
  port (
    address  : in std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
    inclock  : in std_logic;
    data   : in std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
    q  : out std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
    we    : in std_logic
  );
end;

architecture behavioral of ddat_gen is
signal vcc : std_logic := '1';
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
begin
      syncram0 : syncram
        generic map ( depth => address'length, width => data'length)
        port map (
          clk       => inclock,
          address   => address,
          datain    => data,
          dataout   => q,
	  enable    => vcc,
          write     => we
        );
end behavioral;

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity idat_gen is
  port (
    address  : in std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
    inclock  : in std_logic;
    data   : in std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
    q  : out std_logic_vector(IDWORD_BITS + IDPARBITS -1 downto 0);
    we    : in std_logic
  );
end;

architecture behavioral of idat_gen is
signal vcc : std_logic := '1';
component syncram
  generic (
    width : integer := 8;
    depth : integer := 10
  );
  port (
    clk      : in std_logic;
    address  : in std_logic_vector((depth -1) downto 0);
    datain   : in std_logic_vector((width -1) downto 0);
    dataout  : out std_logic_vector((width -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;
begin
      syncram0 : syncram
        generic map ( depth => address'length, width => data'length)
        port map (
          clk   => inclock,
          address   => address,
          datain    => data,
          dataout   => q,
	  enable    => vcc,
          write     => we
        );
end behavioral;

-- pragma translate_on

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity dtag_synp  is
  port (
    address  : in std_logic_vector(DOFFSET_BITS -1 downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
    dataout  : out std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic
  );
attribute syn_isclock : boolean;
attribute syn_isclock of clk : signal is true;
end;

architecture arch0 of dtag_synp is

component dtag_gen
  port (
    address  : in std_logic_vector(DOFFSET_BITS -1 downto 0);
    inclock  : in std_logic;
    data   : in std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
    q  : out std_logic_vector(DTAG_BITS + DTPARBITS -1 downto 0);
    we    : in std_logic
  );
end component;

attribute syn_white_box : boolean;
attribute syn_white_box of dtag_gen : component is true;
--Estimated timing data for -3 speed grade
--Degradation factor ~ 1.25 to estimate timing for a -4 speed grade
attribute syn_scaletiming : string;
attribute syn_scaletiming of dtag_gen : component is "eab_scale";
attribute syn_tsu1 : string;
attribute syn_tsu2 : string;
attribute syn_tsu3 : string;
attribute syn_tco1 : string;
attribute syn_tsu1 of dtag_gen : component is "data[*]->inclock=5.3";
attribute syn_tsu2 of dtag_gen : component is "address[*]->inclock=5.3";
attribute syn_tsu3 of dtag_gen : component is "we->inclock=5.5";
attribute syn_tco1 of dtag_gen : component is "inclock->q[*]=13.7";
attribute LPM_WIDTH : POSITIVE;
attribute LPM_WIDTH of dtag_gen : component is DTAG_BITS + DTPARBITS;
attribute LPM_TYPE : STRING;
attribute LPM_TYPE of dtag_gen : component is "LPM_RAM_DQ";
attribute LPM_WIDTHAD : POSITIVE;
attribute LPM_WIDTHAD of dtag_gen : component is DOFFSET_BITS;
--attribute LPM_NUMWORDS : STRING;
--attribute LPM_NUMWORDS of dtag_gen : component is LPM_NUMWORDS;
attribute LPM_FILE : STRING;
attribute LPM_FILE of dtag_gen : component is "UNUSED";
attribute LPM_INDATA : STRING;
attribute LPM_INDATA of dtag_gen : component is "REGISTERED";
attribute LPM_ADDRESS_CONTROL : STRING;
attribute LPM_ADDRESS_CONTROL of dtag_gen : component is "REGISTERED";
attribute LPM_OUTDATA : STRING;
attribute LPM_OUTDATA of dtag_gen : component is "UNREGISTERED";
attribute LPM_HINT : STRING;
attribute LPM_HINT of dtag_gen : component is "USE_EAB";
attribute altera_area : integer;
attribute altera_area of dtag_gen : component is 0;

signal vcc : std_logic;

begin
  vcc <= '1';
  dtag_gen0 : dtag_gen
    port map (
      inclock       => clk,
      address   => address,
      data    => datain,
      q   => dataout,
      we     => write
    );

end arch0;

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity itag_synp  is
  port (
    address  : in std_logic_vector(IOFFSET_BITS -1 downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
    dataout  : out std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic
  );
attribute syn_isclock : boolean;
attribute syn_isclock of clk : signal is true;
end;

architecture arch0 of itag_synp is

component itag_gen
  port (
    address  : in std_logic_vector(IOFFSET_BITS -1 downto 0);
    inclock      : in std_logic;
    data   : in std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
    q  : out std_logic_vector(ITAG_BITS + ITPARBITS -1 downto 0);
    we    : in std_logic
  );
end component;

attribute syn_white_box : boolean;
attribute syn_white_box of itag_gen : component is true;
--Estimated timing data for -3 speed grade
--Degradation factor ~ 1.25 to estimate timing for a -4 speed grade
attribute syn_scaletiming : string;
attribute syn_scaletiming of itag_gen : component is "eab_scale";
attribute syn_tsu1 : string;
attribute syn_tsu2 : string;
attribute syn_tsu3 : string;
attribute syn_tco1 : string;
attribute syn_tsu1 of itag_gen : component is "data[*]->inclock=5.3";
attribute syn_tsu2 of itag_gen : component is "address[*]->inclock=5.3";
attribute syn_tsu3 of itag_gen : component is "we->inclock=5.5";
attribute syn_tco1 of itag_gen : component is "inclock->q[*]=13.7";
attribute LPM_WIDTH : POSITIVE;
attribute LPM_WIDTH of itag_gen : component is ITAG_BITS + ITPARBITS;
attribute LPM_TYPE : STRING;
attribute LPM_TYPE of itag_gen : component is "LPM_RAM_DQ";
attribute LPM_WIDTHAD : POSITIVE;
attribute LPM_WIDTHAD of itag_gen : component is DOFFSET_BITS;
--attribute LPM_NUMWORDS : STRING;
--attribute LPM_NUMWORDS of itag_gen : component is LPM_NUMWORDS;
attribute LPM_FILE : STRING;
attribute LPM_FILE of itag_gen : component is "UNUSED";
attribute LPM_INDATA : STRING;
attribute LPM_INDATA of itag_gen : component is "REGISTERED";
attribute LPM_ADDRESS_CONTROL : STRING;
attribute LPM_ADDRESS_CONTROL of itag_gen : component is "REGISTERED";
attribute LPM_OUTDATA : STRING;
attribute LPM_OUTDATA of itag_gen : component is "UNREGISTERED";
attribute LPM_HINT : STRING;
attribute LPM_HINT of itag_gen : component is "USE_EAB";
attribute altera_area : integer;
attribute altera_area of itag_gen : component is 0;

signal vcc : std_logic;

begin
  vcc <= '1';
  itag_gen0 : itag_gen
    port map (
      inclock       => clk,
      address   => address,
      data    => datain,
      q   => dataout,
      we     => write
    );

end arch0;


LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;

entity ddat_synp  is
  port (
    address  : in std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
    dataout  : out std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic
  );
attribute syn_isclock : boolean;
attribute syn_isclock of clk : signal is true;
end;

architecture arch0 of ddat_synp is

component ddat_gen
  port (
    address  : in std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
    inclock      : in std_logic;
    data   : in std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
    q  : out std_logic_vector(DDWORD_BITS + DDPARBITS -1 downto 0);
    we    : in std_logic
  );
end component;

attribute syn_white_box : boolean;
attribute syn_white_box of ddat_gen : component is true;
--Estimated timing data for -3 speed grade
--Degradation factor ~ 1.25 to estimate timing for a -4 speed grade
attribute syn_scaletiming : string;
attribute syn_scaletiming of ddat_gen : component is "eab_scale";
attribute syn_tsu1 : string;
attribute syn_tsu2 : string;
attribute syn_tsu3 : string;
attribute syn_tco1 : string;
attribute syn_tsu1 of ddat_gen : component is "data[*]->inclock=5.3";
attribute syn_tsu2 of ddat_gen : component is "address[*]->inclock=5.3";
attribute syn_tsu3 of ddat_gen : component is "we->inclock=5.5";
attribute syn_tco1 of ddat_gen : component is "inclock->q[*]=13.7";
attribute LPM_WIDTH : POSITIVE;
attribute LPM_WIDTH of ddat_gen : component is DDWORD_BITS + DDPARBITS;
attribute LPM_TYPE : STRING;
attribute LPM_TYPE of ddat_gen : component is "LPM_RAM_DQ";
attribute LPM_WIDTHAD : POSITIVE;
attribute LPM_WIDTHAD of ddat_gen : component is DOFFSET_BITS + DLINE_BITS;
--attribute LPM_NUMWORDS : STRING;
--attribute LPM_NUMWORDS of ddat_gen : component is LPM_NUMWORDS;
attribute LPM_FILE : STRING;
attribute LPM_FILE of ddat_gen : component is "UNUSED";
attribute LPM_INDATA : STRING;
attribute LPM_INDATA of ddat_gen : component is "REGISTERED";
attribute LPM_ADDRESS_CONTROL : STRING;
attribute LPM_ADDRESS_CONTROL of ddat_gen : component is "REGISTERED";
attribute LPM_OUTDATA : STRING;
attribute LPM_OUTDATA of ddat_gen : component is "UNREGISTERED";
attribute LPM_HINT : STRING;
attribute LPM_HINT of ddat_gen : component is "USE_EAB";
attribute altera_area : integer;
attribute altera_area of ddat_gen : component is 0;

signal vcc : std_logic;

begin
  vcc <= '1';