pads.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	various pads
-- File:	pads.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	generic and technology specific pads.
------------------------------------------------------------------------------
-- Version control:
-- 16-08-1999:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------


------------------------------------------------------------------
-- Generic pad models --------------------------------------------
------------------------------------------------------------------

-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
entity geninpad is port (pad : in std_logic; q : out std_logic); end; 
architecture rtl of geninpad is begin q <= to_x01(pad); end;

-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
entity gensmpad is port (pad : in std_logic; q : out std_logic); end; 
architecture rtl of gensmpad is begin q <= to_x01(pad); end;

-- output pad
library IEEE;
use IEEE.std_logic_1164.all;
entity genoutpad is port (d : in  std_logic; pad : out  std_logic); end; 
architecture rtl of genoutpad is begin pad <= to_x01(d); end;

-- bidirectional pad
library IEEE;
use IEEE.std_logic_1164.all;
entity geniopad is
  port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end; 
architecture rtl of geniopad is
begin pad <= to_x01(d) when en = '1' else 'Z'; q <= to_x01(pad); end;

-- open-drain pad
library IEEE;
use IEEE.std_logic_1164.all;
entity genodpad is port ( d : in std_logic; pad : out std_logic); end; 
architecture rtl of genodpad is begin pad <= '0' when d = '0' else 'Z'; end;


-- pragma translate_off

------------------------------------------------------------------
-- Mietec pad models --------------------------------------------
------------------------------------------------------------------

-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
entity ibuf is port (a : in std_logic; z : out std_logic); end; 
architecture rtl of ibuf is begin z <= to_x01(a) after 1 ns; end;

-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
entity schmitc is port (a : in std_logic; z : out std_logic); end; 
architecture rtl of schmitc is begin z <= to_x01(a) after 1 ns; end;

-- output pad
library IEEE;
use IEEE.std_logic_1164.all;
entity b8cr is port (a : in  std_logic; z : out  std_logic); end; 
architecture rtl of b8cr is begin z <= to_x01(a) after 4 ns; end;

-- bidirectional pad
library IEEE;
use IEEE.std_logic_1164.all;
entity bd4cr is
  port ( a, en : in std_logic; zi : out std_logic; io : inout std_logic);
end; 
architecture rtl of bd4cr is
begin 
  io <= to_x01(a) after 4 ns when en = '0' else 'Z' after 4 ns;
  zi <= to_x01(io) after 4 ns;
end;

-- bidirectional pad with schmitt input
library IEEE;
use IEEE.std_logic_1164.all;
entity bd8scru is
  port ( a, en : in std_logic; zi : out std_logic; io : inout std_logic);
end; 
architecture rtl of bd8scru is
begin 
  io <= to_x01(a) after 4 ns when en = '0' else 'Z' after 4 ns;
  zi <= to_x01(io) after 4 ns;
end;

-- open-drain pad
library IEEE;
use IEEE.std_logic_1164.all;
entity b8rod is port (a : in std_logic; z : out std_logic); end; 
architecture rtl of b8rod is 
begin
  z <= '0' after 4 ns when a = '0' else 'Z' after 4 ns;
end;

------------------------------------------------------------------
-- Temic MG2 pad models --------------------------------------------
------------------------------------------------------------------

-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
entity bincmos is port (xxx : in std_logic; o : out std_logic); end; 
architecture rtl of bincmos is begin o <= to_x01(xxx) after 1 ns; end;

-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
entity btgcmos is port (xxx : in std_logic; o : out std_logic); end; 
architecture rtl of btgcmos is begin o <= to_x01(xxx) after 1 ns; end;

-- output pad
library IEEE;
use IEEE.std_logic_1164.all;
entity boutq is port (i : in  std_logic; xxx : out  std_logic); end; 
architecture rtl of boutq is begin xxx <= to_x01(i) after 4 ns; end;

-- bidirectional pad
library IEEE;
use IEEE.std_logic_1164.all;
entity biocq is
  port ( i, e : in std_logic; o : out std_logic; xxx : inout std_logic);
end; 
architecture rtl of biocq is
begin 
  xxx <= to_x01(i) after 4 ns when e = '1' else 'Z' after 4 ns;
  o <= to_x01(i) after 4 ns;
end;

-- bidirectional pad with schmitt input
library IEEE;
use IEEE.std_logic_1164.all;
entity biotgc12 is
  port ( i, e : in std_logic; o : out std_logic; xxx : inout std_logic);
end; 
architecture rtl of biotgc12 is
begin 
  xxx <= to_x01(i) after 4 ns when e = '1' else 'Z' after 4 ns;
  o <= to_x01(i) after 4 ns;
end;

-- pragma translate_on

------------------------------------------------------------------
-- Pad package
------------------------------------------------------------------

LIBRARY ieee;
use IEEE.std_logic_1164.all; 

package padlib is
component geninpad port (pad : in std_logic; q : out std_logic); end component; 
component gensmpad port (pad : in std_logic; q : out std_logic); end component;
component genoutpad port (d : in  std_logic; pad : out  std_logic); end component; 
component geniopad 
  port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component genodpad port ( d : in std_logic; pad : out std_logic); end component;

component ibuf port (a : in std_logic; z : out std_logic); end component; 
component schmitc port (a : in std_logic; z : out std_logic); end component;
component b8cr port (a : in  std_logic; z : out  std_logic); end component; 
component bd4cr 
  port ( a, en : in std_logic; zi : out std_logic; io : inout std_logic);
end component; 
component bd8scru
  port ( a, en : in std_logic; zi : out std_logic; io : inout std_logic);
end component; 
component b8rod port (a : in std_logic; z : out std_logic); end component; 

component bincmos port (xxx : in std_logic; o : out std_logic); end component; 
component btgcmos port (xxx : in std_logic; o : out std_logic); end component; 
component boutq port (i : in  std_logic; xxx : out  std_logic); end component; 
component biocq 
  port ( i, e : in std_logic; o : out std_logic; xxx : inout std_logic);
end component; 
component biotgc12 
  port ( i, e : in std_logic; o : out std_logic; xxx : inout std_logic);
end component;

end padlib;



------------------------------------------------------------------
-- Pad models with technology selection --------------------------
------------------------------------------------------------------

-- input pad

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.padlib.all;

entity inpad is port (pad : in std_logic; q : out std_logic); end; 

architecture rtl of inpad is
begin
  ip0: if TARGET_TECH = mietec generate
    ibuf0: ibuf port map (a => pad, z => q);
  end generate;
  ip1: if (TARGET_TECH = none) or (TARGET_TECH = altera) generate
    ginpad0 : geninpad port map (q => q, pad => pad);
  end generate;
  ip2 : if TARGET_TECH = mg2 generate
    bincmos0 : bincmos port map (o => q, xxx => pad);
  end generate;
end;

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.padlib.all;

entity smpad is port (pad : in std_logic; q : out std_logic); end; 

architecture rtl of smpad is
begin
  sm0: if TARGET_TECH = mietec generate
    schmitc0: schmitc port map (a => pad, z => q);
  end generate;
  sm1: if (TARGET_TECH = none) or (TARGET_TECH = altera) generate
    gsmpad0 : gensmpad port map (q => q, pad => pad);
  end generate;
  sm2 : if TARGET_TECH = mg2 generate
    btgcmos0 : btgcmos port map (o => q, xxx => pad);
  end generate;
end;

-- output pad

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.padlib.all;

entity outpad is port (d : in std_logic; pad : out std_logic); end; 

architecture rtl of outpad is
begin
  op0: if TARGET_TECH = mietec generate
    b8cr0: b8cr port map (a => d, z => pad);
  end generate;
  op1: if (TARGET_TECH = none) or (TARGET_TECH = altera) generate
    goutpad0 : genoutpad port map (d => d, pad => pad);
  end generate;
  op2 : if TARGET_TECH = mg2 generate
    boutq0 : boutq port map (i => d, xxx => pad);
  end generate;
end;

-- bidirectional pad

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.padlib.all;

entity iopad is
  port (
    d     : in  std_logic;
    en    : in  std_logic;
    q     : out std_logic;
    pad   : inout std_logic
  );
end; 

architecture rtl of iopad is
signal eni : std_logic;
begin
  iop0: if TARGET_TECH = mietec generate
    eni <= not en;
    bd4cr0 : bd4cr port map (a => d, en => eni, zi => q, io => pad);
  end generate;
  iop1: if (TARGET_TECH = none) or (TARGET_TECH = altera) generate
    giop0 : geniopad port map (d => d, en => en, q => q, pad => pad);
  end generate;
  iop2 : if TARGET_TECH = mg2 generate
    biocq0 : biocq port map (i => d, e => en, o => q, xxx => pad);
  end generate;
end;

-- bidirectional pad with schmitt trigger for I/O ports

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.padlib.all;

entity smiopad is
  port (
    d     : in  std_logic;
    en    : in  std_logic;
    q     : out std_logic;
    pad   : inout std_logic
  );
end; 

architecture rtl of smiopad is
signal eni : std_logic;
begin
  smiop0 : if TARGET_TECH = mietec generate
    eni <= not en;
    bd8scru0 : bd8scru port map (a => d, en => eni, zi => q, io => pad);
  end generate;
  smiop1 : if (TARGET_TECH = none) or (TARGET_TECH = altera) generate
    giop0 : geniopad port map (d => d, en => en, q => q, pad => pad);
  end generate;
  smiop2 : if TARGET_TECH = mg2 generate
    biotgc12_0 : biotgc12 port map (i => d, e => en, o => q, xxx => pad);
  end generate;
end;

-- open-drain pad

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.padlib.all;
 
entity odpad is
  port (
    d     : in  std_logic;
    pad   : out  std_logic
  );
end; 

architecture rtl of odpad is
signal en, lp : std_logic;
begin
  odp0 : if TARGET_TECH = mietec generate 
    b8rod0: b8rod port map (a => d, z => pad);
  end generate;
  odp1 : if (TARGET_TECH = none) or (TARGET_TECH = altera) generate
    godpad0 : genodpad port map (d => d, pad => pad);
  end generate;
  odp2 : if TARGET_TECH = mg2 generate
    en <= not d; pad <= lp;
    biotgc12_0 : biotgc12 port map (i => d, e => en, o => open, xxx => lp);
  end generate;
end;

library IEEE;
use IEEE.std_logic_1164.all;
use work.iface.all;
 
entity pads is
  port (
  clki	    : in    std_logic;
  clko	    : out   std_logic;
  resetni   : in    std_logic;
  resetno   : out   std_logic;
  errorn    : in    std_logic;
  data      : inout std_logic_vector(31 downto 0);
  cb        : inout std_logic_vector(6 downto 0);
  piol      : inout std_logic_vector(15 downto 0);
  padin	    : in    pad_in_type;
  padout    : out   pad_out_type;
  memi	    : out   memory_in_type;
  memo	    : in    memory_out_type;
  ioi	    : out	io_in_type;
  ioo	    : in 	io_out_type
  );
end; 
 
architecture rtl of pads is

component inpad port (pad : in std_logic; q : out std_logic); end component;
component smpad port (pad : in std_logic; q : out std_logic); end component;
component outpad port (d : in std_logic; pad : out std_logic); end component;
component odpad port (d : in std_logic; pad : out std_logic); end component;

component iopad
  port (
    d     : in  std_logic;
    en    : in  std_logic;
    q     : out std_logic;
    pad   : inout std_logic
  );
end component;


begin

--  inpad0   : inpad port map (clki, clko);	-- clock
  clko <= clki;					-- avoid buffering during synthesis
  smpad0   : smpad port map (resetni, resetno);	-- reset

  inpad2   : inpad port map (padin.brdyn, memi.brdyn);	-- bus ready
  inpad3   : inpad port map (padin.bexcn, memi.bexcn);	-- bus exception

  outpad0   : odpad port map (errorn, padout.errorn);	-- cpu error mode

  iopadb0: for i in 24 to 31 generate			-- data bus
    iopadb01: iopad port map (memo.data(i), memo.bdrive(0), memi.data(i), data(i));
  end generate;

  iopadb1: for i in 16 to 23 generate
    iopadb11: iopad port map (memo.data(i), memo.bdrive(1), memi.data(i), data(i));
  end generate;

  iopadb2: for i in 8 to 15 generate
    iopadb21: iopad port map (memo.data(i), memo.bdrive(2), memi.data(i), data(i));
  end generate;

  iopadb3: for i in 0 to 7 generate
    iopadb31: iopad port map (memo.data(i), memo.bdrive(3), memi.data(i), data(i));
  end generate;

  iopadb4: for i in 0 to 6 generate		-- memory checkbits
    iopadb41: iopad port map (memo.checkbits(i), memo.bdrive(3), memi.checkbits(i), cb(i));
  end generate;

  iopadb5: for i in 0 to 15 generate		-- parallel I/O port
    iopadb51: iopad port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), piol(i));
  end generate;

  outpadb0: for i in 0 to 27 generate			-- memory address
    outpadb01: outpad port map (memo.address(i), padout.address(i));
  end generate;

  outpadb1: for i in 0 to 3 generate			-- ram oen/rasn
    outpadb11: outpad port map (memo.ramsn(i), padout.ramsn(i));
  end generate;

  outpadb2: for i in 0 to 3 generate			-- ram chip select
    outpadb21: outpad port map (memo.ramoen(i), padout.ramoen(i));
  end generate;

  outpadb3: for i in 0 to 1 generate			-- rom chip select
    outpadb31: outpad port map (memo.romsn(i), padout.romsn(i));
  end generate;

  outpadb4: for i in 0 to 3 generate			-- ram write strobe
    outpadb41: outpad port map (memo.wrn(i), padout.rwen(i));
  end generate;

  outpadb5: outpad port map (memo.read, padout.read);	-- memory read
  outpadb6: outpad port map (memo.oen, padout.oen);	-- memory oen
  outpadb7: outpad port map (memo.iosn, padout.iosn);	-- I/O select
  outpadb8: outpad port map (memo.writen, padout.writen);-- I/O write

  outpadb9: odpad port map (ioo.wdog, padout.wdogn);	-- watchdog output
end;