proc.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	proc
-- File:	proc.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	This unit contains the integer unit, cache memory and 
--		clock/reset generation.
------------------------------------------------------------------------------
-- Version control:
-- 11-9-1998:	First implemetation
-- 26-9-1999:	Release 1.0
------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;

entity proc is
  port (
    rst      : in  std_logic;
    clk      : in  std_logic;
    mcii : out memory_ic_in_type;
    mcio : in  memory_ic_out_type;
    mcdi : out memory_dc_in_type;
    mcdo : in  memory_dc_out_type;
    sysi   : in  sys_in_type;
    syso   : out sys_out_type;
    rstout   : out std_logic;
    clkout   : out std_logic
-- pragma translate_off
    ;debug  : out iu_debug_type
-- pragma translate_on
  );
end; 

architecture rtl of proc is

component clkgen 
port (
    rst      : in  std_logic;
    clk      : in  std_logic;
    clki   : in  clk_in_type;
    clko   : out clk_out_type
);
end component;

component iu
port (
    rst    : in  std_logic;			-- Reset
    clk    : in  std_logic;			-- main clock
    iclk   : in  std_logic;			-- missed instruction clock
    dclk   : in  std_logic;			-- missed data clock
    holdn  : in  std_logic;			-- pipeline hold
    ici    : out icache_in_type;
    ico    : in  icache_out_type;
    dci    : out dcache_in_type;
    dco    : in  dcache_out_type;
    rfi    : out rf_in_type;			-- register-file input
    rfo    : in  rf_out_type;			-- register-file output
    sysi   : in  sys_in_type;
    syso   : out sys_out_type
-- pragma translate_off
    ;debug  : out iu_debug_type
-- pragma translate_on
  );
end component;

component regfile
  port (
    Clk   : in  std_logic;                       -- Clock
    holdn : in  std_logic;
    rfi   : in  rf_in_type;
    rfo   : out rf_out_type
  );
end component;

component cache
  port (
    rst   : in  std_logic;
    clk   : in  std_logic;
    ici   : in  icache_in_type;
    ico   : out icache_out_type;
    dci   : in  dcache_in_type;
    dco   : out dcache_out_type;
    mcii  : out memory_ic_in_type;
    mcio  : in  memory_ic_out_type;
    mcdi  : out memory_dc_in_type;
    mcdo  : in  memory_dc_out_type
  );
end component; 

signal clki : clk_in_type;
signal clko : clk_out_type;
signal clkol : clk_out_type;
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;

signal rfi : rf_in_type;			-- register-file input
signal rfo : rf_out_type;			-- register-file output

 
begin

-- clock and reset generation

  cgen0 : if not GATEDCLK generate
    clkgen0 : clkgen port map (
	rst  => rst, clk  => clk, clki => clki, clko => clkol
    );
    clko.holdn  <= clkol.holdn;
    clko.reset  <= clkol.reset;
    clko.clk    <= clk;
    clko.cpuclk <= clk;
    clko.iclk   <= clk;
    clko.dclk   <= clk;
    clkout      <= clk;
  end generate;

  cgen1 : if GATEDCLK generate
    clkgen0 : clkgen port map (
      rst  => rst, clk  => clk, clki => clki, clko => clkol
    );
    clkout      <= clko.clk;
    clko        <= clkol;
  end generate;

  rstout      <= clko.reset;
  clki.iholdn <= ico.hold;
  clki.imdsn  <= ico.mds;
  clki.dholdn <= dco.hold;
  clki.dmdsn  <= dco.mds;

-- processor core

  iu0 : iu  port map ( 
	Rst => clko.reset, clk => clko.cpuclk, Dclk => clko.dclk, 
	Iclk => clko.iclk, holdn => clko.holdn,
	ici => ici, ico => ico, dci => dci, dco => dco, 
	rfi => rfi, rfo => rfo, sysi => sysi, syso => syso
-- pragma translate_off
	, debug => debug
-- pragma translate_on
  );

-- register file
  regfile0 : regfile port map (
	clk	=> clko.cpuclk,
	holdn	=> clko.holdn,
	rfi	=> rfi,
	rfo	=> rfo
  );

-- cacahe memory

  c0 : cache port map (rst, clko.clk, ici, ico, dci, dco, mcii, mcio, mcdi, mcdo);

end ;