ioport.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	ioport
-- File:	ioport.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Parallel I/O port. On reset, all port are programmed as
--		inputs and remaning registers are unknown. This means
--		that the interrupt configuration registers must be
--		written before I/O port interrputs are unmasked in the
--		interrupt controller.
------------------------------------------------------------------------------
-- Version control:
-- 11-10-1998:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed."-";
use work.iface.all;
use work.macro.genmux;
 
entity ioport is
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    pbo    : out pbus_out_type;
    uart1o : in  uart_out_type;
    uart2o : in  uart_out_type;
    pei    : in  peri_in_type;
    pioo   : out pio_out_type
  );
end; 
 
architecture rtl of ioport is

type irq_ctrl_type is record
  isel	 : std_logic_vector(4 downto 0);
  pol    : std_logic;
  edge   : std_logic;
  enable : std_logic;
end record;

type irq_conf_type is array (3 downto 0) of irq_ctrl_type;

type pioregs is record
  irqout	:  std_logic_vector(3 downto 0);
  irqlat	:  std_logic_vector(3 downto 0);
  pin1      	:  std_logic_vector(15 downto 0);
  pin2		:  std_logic_vector(31 downto 0);
  pdir		:  std_logic_vector(15 downto 0);
  pout		:  std_logic_vector(15 downto 0);
  iconf 	:  irq_conf_type;
end record;

signal r, rin : pioregs;

begin

  pioop : process(rst, r, pbi, pei, uart1o, uart2o)
  variable rdata : std_logic_vector(31 downto 0);
  variable v : pioregs;
  begin

    v := r; 

-- synchronise port inputs. Low 16 bits are latched twice while high 16 bits
-- are allready latched once in the memory controller and therefore only
-- latched once here.

    v.pin1 := pei.piol; v.pin2 := pbi.pioh & r.pin1;

-- read/write registers

    rdata := (others => '0');
    if pbi.enable = '1' then
      if pbi.read = '1' then
	case pbi.address is
	when "101000" => rdata(31 downto 0) := r.pin2;
	when "101001" => rdata(15 downto 0) := r.pdir;
	when "101010" => rdata(31 downto 0) := 
	  r.iconf(3).enable & r.iconf(3).edge & r.iconf(3).pol & r.iconf(3).isel &
	  r.iconf(2).enable & r.iconf(2).edge & r.iconf(2).pol & r.iconf(2).isel &
	  r.iconf(1).enable & r.iconf(1).edge & r.iconf(1).pol & r.iconf(1).isel &
	  r.iconf(0).enable & r.iconf(0).edge & r.iconf(0).pol & r.iconf(0).isel;
  	when others => null;
	end case;
      else
	case pbi.address is
	when "101000" =>  v.pout := pbi.data(15 downto 0);
	when "101001" =>  v.pdir := pbi.data(15 downto 0);
	when "101010" =>  
	  v.iconf(3).enable := pbi.data(31); v.iconf(3).edge := pbi.data(30);
	  v.iconf(3).pol := pbi.data(29); v.iconf(3).isel := pbi.data(28 downto 24);
	  v.iconf(2).enable := pbi.data(23); v.iconf(2).edge := pbi.data(22);
	  v.iconf(2).pol := pbi.data(21); v.iconf(2).isel := pbi.data(20 downto 16);
	  v.iconf(1).enable := pbi.data(15); v.iconf(1).edge := pbi.data(14);
	  v.iconf(1).pol := pbi.data(13); v.iconf(1).isel := pbi.data(12 downto 8);
	  v.iconf(0).enable := pbi.data(7); v.iconf(0).edge := pbi.data(6);
	  v.iconf(0).pol := pbi.data(5); v.iconf(0).isel := pbi.data(4 downto 0);
	when others => null;
 	end case;
      end if;
    end if;

-- interrupt generation

    for i in 0 to 3 loop	-- select and latch interrupt source
      v.irqlat(i) := genmux(r.iconf(i).isel, r.pin2);
  
      if r.iconf(i).enable = '1' then
      	if r.iconf(i).edge = '1' then
	  v.irqout(i) := (v.irqlat(i) xor r.irqlat(i)) and 
		       (v.irqlat(i) xor not r.iconf(i).pol);
        else
	  v.irqout(i) := (v.irqlat(i) xor not r.iconf(i).pol);
	end if;
      else
	v.irqout(i) := '0';
      end if;
    end loop;

-- reset operation

    if rst = '0' then 
      v.pdir := (others => '0');
      v.iconf(0).enable := '0'; v.iconf(1).enable := '0';
      v.iconf(2).enable := '0'; v.iconf(3).enable := '0';
    end if;

-- drive signals

    rin <= v; 		-- update registers
    pbo.data <= rdata; 	-- drive data bus
    pioo.irq      <= r.irqout;
    pioo.piodir   <= r.pdir;
    pioo.romwidth <= r.pin2(1 downto 0);
    pioo.romedac  <= r.pin2(2);
    pioo.rxd(0)   <= r.pin2(14);
    pioo.ctsn(0)  <= r.pin2(12);
    pioo.rxd(1)   <= r.pin2(10);
    pioo.ctsn(1)  <= r.pin2(8);
    pioo.piol(14)  <= r.pout(14);
    pioo.piol(12)  <= r.pout(12);
    pioo.piol(10)  <= r.pout(10);
    pioo.piol(8 downto 0) <= r.pout(8 downto 0);
    
    -- override I/O port settings if UARTs are enabled
    pioo.piol(15) <= 
	((not uart1o.txen) and r.pout(15)) or (uart1o.txen and uart1o.txd);
    pioo.piol(13) <= 
	((not uart1o.flow) and r.pout(13)) or (uart1o.flow and uart1o.rtsn);
    pioo.piol(11) <= 
	((not uart2o.txen) and r.pout(11)) or (uart2o.txen and uart2o.txd);
    pioo.piol( 9) <= 
	((not uart2o.flow) and r.pout( 9)) or (uart2o.flow and uart2o.rtsn);

  end process;

-- registers

  regs : process(clk)
  begin
    if clk'event and (clk = '1') then
      r <= rin;
    end if;
  end process;


end;