clkgen.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	clkgen
-- File:	clkgen.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	This unit implemets the clock generation for the processor
--		and all peripherals. Four clocks are generated: a common
--		uninterrupted clock (clko.clk), a processor clock (clko.cpuclk),
--		a clock to latch a missed instruction (clko.iclk) and a clock
--		to latch missed data (clk0.dclk). Clock generation depends on 
--              the constant GATEDCLK defined in config.vhd. If it is NOT set,
--		all clocks will run uninterrupted and muxes will be used
--		to halt the processor during cache misses.
--
--		Internal reset is also generated by this unit.

------------------------------------------------------------------------------
-- Version control:
-- 11-10-1998:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;

entity clkgen is
port (
    rst      : in  std_logic;
    clk      : in  std_logic;
    clki   : in  clk_in_type;
    clko   : out clk_out_type
);
end;

architecture rtl of clkgen is
signal dclkholdn, iclkholdn, cpuclkholdn : std_logic;
signal rstr : std_logic_vector(3 downto 0);
signal rstv : std_logic_vector(3 downto 0);
signal rstf : std_logic_vector(2 downto 0);

begin


-- reset generation

  reg1 : process (clk)
  begin
    if clk'event and (clk = '1') then
      rstf <= rstf(1 downto 0) & rst;
      rstr <= rstv;
    end if;
  end process;

  clko.reset <= rstr(3);
  rstv <= "1111" when (rstf(2 downto 1) = "11") else rstr(2 downto 0) & '0';

-- processor clk generation

  reg2 : process (clk)
  begin
    if clk'event and (clk = '0') then
      dclkholdn <= (clki.iholdn and clki.dholdn) or not clki.dmdsn;
      iclkholdn <= (clki.iholdn and clki.dholdn) or not clki.imdsn;
      cpuclkholdn <= clki.iholdn and clki.dholdn;
    end if;
  end process;

  clko.dclk <= clk and dclkholdn when GATEDCLK else clk;
  clko.iclk <= clk and iclkholdn when GATEDCLK else clk;
  clko.cpuclk <= clk and cpuclkholdn when GATEDCLK else clk;

  clko.clk <= clk;

  clko.holdn <= clki.iholdn and clki.dholdn;
  

end;