mcore.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	mcore
-- File:	mcore.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Contains the complete processor except for the pads
------------------------------------------------------------------------------
-- Version control:
-- 17-02-1999:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;

entity mcore is
  port (
    rst      : in  std_logic;
    clk      : in  std_logic;
    error    : out std_logic;
    memi     : in  memory_in_type;
    memo     : out memory_out_type;
    ioi      : in  io_in_type;
    ioo      : out io_out_type
-- pragma translate_off
    ;debug  : out iu_debug_type
-- pragma translate_on
  );
end; 

architecture rtl of mcore is

component proc
  port (
    rst      : in  std_logic;
    clk      : in  std_logic;
    mcii : out memory_ic_in_type;
    mcio : in  memory_ic_out_type;
    mcdi : out memory_dc_in_type;
    mcdo : in  memory_dc_out_type;
    sysi   : in  sys_in_type;
    syso   : out sys_out_type;
    rstout   : out std_logic;
    clkout   : out std_logic
-- pragma translate_off
    ;debug  : out iu_debug_type
-- pragma translate_on
  );
end component; 

component mctrl
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    mcii   : in  memory_ic_in_type;
    mcio   : out memory_ic_out_type;
    mcdi   : in  memory_dc_in_type;
    mcdo   : out memory_dc_out_type;
    mcmi   : in  memory_dma_in_type;
    mcmo   : out memory_dma_out_type;
    memi   : in  memory_in_type;
    memo   : out memory_out_type;
    pbi    : out pbus_in_type;
    pbo    : in  pbus_out_type;
    peo    : in  peri_out_type;
    syso   : in  sys_out_type;
    mctrli : in  mctrl_in_type;
    mctrlo : out mctrl_out_type
  );
end component; 

component dma
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    mcmi   : out memory_dma_in_type;
    mcmo   : in  memory_dma_out_type
  );
end component; 

component peri
port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    pbo    : out pbus_out_type;
    pei    : in  peri_in_type;
    peo    : out peri_out_type
  );
end component; 

signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal mcmi : memory_dma_in_type;
signal mcmo : memory_dma_out_type;
signal pei  : peri_in_type;
signal peo  : peri_out_type;
signal pbi  : pbus_in_type;
signal pbo  : pbus_out_type;
signal sysi : sys_in_type;
signal syso : sys_out_type;
signal mctrli : mctrl_in_type;
signal mctrlo : mctrl_out_type;
signal rstout : std_logic;
signal clkout : std_logic;
 
begin


  sysi.irl <= peo.irl; 

-- processor sub-system

  proc0 : proc port map ( rst, clk, mcii, mcio, mcdi, mcdo, sysi, syso, 
			  rstout, clkout
-- pragma translate_off
			, debug
-- pragma translate_on
  );

-- memory controller

  mctrl0 : mctrl port map (
	rst => rstout, clk=> clkout, mcii => mcii, mcio => mcio, 
	mcdi => mcdi, mcdo => mcdo, mcmi => mcmi, mcmo => mcmo, 
	memi => memi, memo => memo, pbi => pbi, pbo => pbo, peo => peo, 
	syso => syso, mctrli => mctrli, mctrlo => mctrlo
  );

-- DMA (simulation only)

  dma0 : dma port map (
	rst => rstout, clk=> clkout, pbi => pbi, mcmi => mcmi, mcmo => mcmo
  );

-- peripherals

  peri0 : peri port map (
	rst => rstout, clk => clkout, 
	pbi => pbi, pbo => pbo, pei => pei, peo => peo
  );


  pei.iv      <= syso.irqvec;
  pei.piol     <= ioi.piol;
  pei.intack  <= syso.intack;
  pei.cerror  <= mctrlo.cerror;
  mctrli.romwidth <= peo.romwidth;
  mctrli.romedac  <= peo.romedac;
  ioo.piol <= peo.piol(15 downto 0);
  ioo.piodir <= peo.piodir(15 downto 0);
  ioo.wdog <= peo.wdog;
  error <= syso.error;

end ;