regfile.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	regfile
-- File:	regfile.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Register file. The real implementations are in ramlib, this
--		module only selects implementation according to which
--		TARGET_TECH is defined.
------------------------------------------------------------------------------
-- Version control:
-- 11-10-1998:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;
use work.ramlib.all;

entity regfile is
  port (
    Clk  : in  std_logic;			-- Clock
    holdn  : in  std_logic;
    rfi  : in  rf_in_type;
    rfo  : out rf_out_type
  );
end;

architecture behav of regfile is

begin
  behav : if TARGET_TECH = none generate 	-- Generic register file
    rfgen0 : rfgen port map (Clk, holdn, rfi, rfo);
  end generate;

  alt : if TARGET_TECH = altera generate 
    altera_synplify : if SYNTOOL = synplify generate
      rfaltsynp0 : rfaltsynp port map (Clk, holdn, rfi, rfo);
    end generate;
    altera_synopsys : if SYNTOOL = synopsys generate
      rfaltsyno0 : rfaltsyno port map (Clk, holdn, rfi, rfo);
    end generate;
    altera_leonardo : if SYNTOOL = leonardo generate
      rfaltsyno0 : rfaltleo port map (Clk, holdn, rfi, rfo);
    end generate;
  end generate;

  temic : if (TARGET_TECH = mg2) or (TARGET_TECH = mietec) generate 
    temic_synopsys : if SYNTOOL = synopsys generate
      rfaltsyno0 : rfaltsyno port map (Clk, holdn, rfi, rfo);
    end generate;
  end generate;

end;