add_sub.v

11,13,16位超前进位加法器的Verilog HDL源代码。

`timescale 1ns/100ps

module  ALU_16bit(SRC0, SRC1, SUB, SUM);
input  [15:0] SRC0, SRC1;
input  SUB;
output [16:0] SUM;

wire	[15:0] a, b, G, P;
wire    [3:0]  G1, P1;
wire    [4:1]  Cx;
wire    [16:1] Ct;
wire    [16:0] C;

assign	a = SRC0;
assign	b = SUB ? (~SRC1) : SRC1; 

assign  G = a & b;
assign  P = a | b;

CLA_4bit U1(a[3:0],b[3:0],SUB,Ct[4:1],G1[0],P1[0]);
CLA_4bit U2(a[7:4],b[7:4],Cx[1],Ct[8:5],G1[1],P1[1]);
CLA_4bit U3(a[11:8],b[11:8],Cx[2],Ct[12:9],G1[2],P1[2]);
CLA_4bit U4(a[15:12],b[15:12],Cx[3],Ct[16:13],G1[3],P1[3]);

CLA_4bit U5(G1[3:0],P1[3:0],SUB,Cx[4:1], ,);

assign C = {Cx[4],Ct[15:13],Cx[3],Ct[11:9],Cx[2],Ct[7:5],Cx[1],Ct[3:1],SUB};
assign SUM = G ^ P ^ C;

endmodule


module CLA_4bit(G, P, Ci, Co, G1, P1);
input  [3:0] G, P;
input  Ci;
output [4:1] Co;
output G1, P1;

assign Co[1] = G[0] | P[0]&Ci;
assign Co[2] = G[1] | P[1]&G[0] | P[1]&P[0]&Ci;
assign Co[3] = G[2] | P[2]&G[1] | P[2]&P[1]&G[0] | P[2]&P[1]&P[0]&Ci;
assign Co[4] = G1 | P1&Ci;

assign G1 = G[3] | P[3]&G[2] | P[3]&P[2]&G[1] | P[3]&P[2]&P[1]&G[0];
assign P1 = P[3]&P[2]&P[1]&P[0];

endmodule


module  ALU_11bit(SRC0, SRC1, SUB, SUM);
input  [10:0] SRC0, SRC1;
input  SUB;
output [11:0] SUM;

wire	[10:0] a, b, G, P;
wire    [2:0]  G1, P1;
wire    [3:1]  Cx;
wire    [11:1] Ct;
wire    [11:0] C;

assign	a = SRC0;
assign	b = SUB ? (~SRC1) : SRC1; 

assign  G = a & b;
assign  P = a | b;

CLA_3bit U1(a[2:0],b[2:0],SUB,Ct[3:1],G1[0],P1[0]);
CLA_4bit U2(a[6:3],b[6:3],Cx[1],Ct[7:4],G1[1],P1[1]);
CLA_4bit U3(a[10:7],b[10:7],Cx[2],Ct[11:8],G1[2],P1[2]);

CLA_3bit U4(G1[2:0],P1[2:0],SUB,Cx[3:1], ,);

assign C = {Cx[3],Ct[10:8],Cx[2],Ct[6:4],Cx[1],Ct[2:1],SUB};
assign SUM = G ^ P ^ C;

endmodule


module  ALU_13bit(SRC0, SRC1, SUB, SUM);
input  [12:0] SRC0, SRC1;
input  SUB;
output [13:0] SUM;

wire	[12:0] a, b, G, P;
wire    [3:0]  G1, P1;
wire    [4:1]  Cx;
wire    [13:1] Ct;
wire    [13:0] C;

assign	a = SRC0;
assign	b = SUB ? (~SRC1) : SRC1; 

assign  G = a & b;
assign  P = a | b;

CLA_3bit U1(a[2:0],b[2:0],SUB,Ct[3:1],G1[0],P1[0]);
CLA_3bit U2(a[5:3],b[5:3],Cx[1],Ct[6:4],G1[1],P1[1]);
CLA_3bit U3(a[8:6],b[8:6],Cx[2],Ct[9:7],G1[2],P1[2]);
CLA_4bit U4(a[12:9],b[12:9],Cx[3],Ct[13:10],G1[3],P1[3]);

CLA_4bit U5(G1[3:0],P1[3:0],SUB,Cx[4:1], ,);

assign C = {Cx[4],Ct[12:10],Cx[3],Ct[8:7],Cx[2],Ct[5:4],Cx[1],Ct[2:1],SUB};
assign SUM = G ^ P ^ C;

endmodule

module CLA_3bit(G, P, Ci, Co, G1, P1);
input  [2:0] G, P;
input  Ci;
output [3:1] Co;
output G1, P1;

assign Co[1] = G[0] | P[0]&Ci;
assign Co[2] = G[1] | P[1]&G[0] | P[1]&P[0]&Ci;
assign Co[3] = G1 | P1&Ci;

assign G1 = G[2] | P[2]&G[1] | P[2]&P[1]&G[0];
assign P1 = P[2]&P[1]&P[0];

endmodule