alu.tlg

这些是verilog编程实例5,仅供参考

Selecting top level module alu
Synthesizing module alu
@W:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":28:4:28:7|Latch generated from always block for signal outp_a[7:0], probably caused by a missing assignment in an if or case stmt